ASKiIMAN™ CODEX // COMPUTER ARCHITECTURE, NETWORKS & DIGITAL SYSTEMS (12 UNIFIED CHAPTERS)

The Silicon Codex

PILLAR FILTER:

◈ SEMANTIC ASCII-CSS COMPUTER ARCHITECTURE OBSERVATORY // CLICK ANY DOMAIN TO JUMP ◈ 🐾 PRESS [ / ] TO SEARCH · [ [ ] & [ ] ] TO STEP CHAPTERS

   🖥️ [PARAM]
  1991 PARAM 8000
  AIRAWAT · NSM
  [EXASCALE 10¹⁸]

01. SUPERCOMP PARAM & NSM

   ⚙️ [VON NEUMANN]
  +-------------+
  | CU ⇄ ALU    |
  | [REGISTERS] |
  +-------------+

02. CPU-5GENS 5 Gens & CPU

      /\ Reg
     /L1\ Cache
    /RAM \ DRAM
   /SSD·HD\ Aux

03. MEMORY Cache, RAM/ROM

   0101 ──► [NAND]
   Base 2·8·10·16
   2's Complement
  [LOGIC GATES]

04. BINARY-GATE Radix & Gates

   [SOURCE CODE]
     │ Compiler
     ▼ / Interp.
   [OS KERNEL]

05. OS-LANGS Kernel & Code

   🌐 [OSI 7-LYR]
  7.App ──► 4.TCP
  3.IP  ──► 2.MAC
  1.Physical Bits

06. OSI-NETS OSI & TCP/IP

   🛡️ [CYBER-AI]
  Virus·Worm·Troj
  Firewall · SSL
  Cloud & Neural

07. CYBER-AI Malware & AI

   ⚡ [VAULT]
  +-----------+
  | 24 SILICON|
  | ICT TRAPS |
  +-----------+

08. 24-TRAPS Prelims Vault

I. Silicon Genesis, Supercomputing (PARAM) & Quantum Computing (Ch 01–03)[🖥️ PARAM · NSM · QUANTUM]

01SILICON-GENESISI/O Cycle & Early PARAM 02SUPERCOMPUTERSNSM, AIRAWAT & Exascale 03QUANTUM-CLASSQubits, Pioneers & Types

II. Five Generations, CPU Architecture, Memory Pyramid & Logic Gates (Ch 04–05, 09)[⚙️ 5 GENS · CPU · MEMORY · GATES]

04GENERATIONS-CPU5 Generations, CPU & I/O 05MEMORY-STORAGERAM/ROM, Cache & Units 09BINARY-GATESRadix, ASCII & Logic Gates

III. Software, OS Kernel, Programming Languages, DBMS & Office Suite (Ch 06, 10)[💻 OS KERNEL · COMPILER · SQL · OFFICE]

06SOFTWARE-LANGSOS, Compilers & Languages 10DBMS-OFFICESQL, Excel & Shortcuts

IV. Computer Networks, OSI/TCP-IP, Cybersecurity, AI & Silicon Lexicon (Ch 07–08, 11)[🌐 OSI 7-LAYER · CYBER · AI · PORTS]

07NETWORKS-OSIOSI 7-Layer, TCP/IP & Web 08CYBER-AI-CLOUDMalware, Security & AI 11LEXICON-PORTS100+ Acronyms & Ports

V. Master Reference & Prelims Deep-Dive Vault (Ch 12)[⚡ 24 PRELIMS ICT TRAPS]

12DEEP-DIVES24 Prelims Traps

CH 01 · SILICON-GENESIS // I. Silicon Genesis, Supercomputing (PARAM) & Quantum Computing (Ch 01–03)CH 01 · DATA PROCESSING CYCLE, QUANTUM OF MEMORY & INDIA’S EARLY MAINFRAMES (1956–2002)

The Silicon Genesis: Architecture of Logic, Indian Mainframes (HEC-2M, TIFRAC) & PARAM Dawn

Input-Process-Output Alchemy, Bit/Nibble/Byte Foundations, 1956 ISI Kolkata HEC-2M, 1962 TIFRAC & C-DAC’s PARAM 8000 to Padma

RADAR:Input → Process → Output → InformationBit (0/1) · Nibble (4 Bits) · Byte (8 Bits = 1 Character)1956 HEC-2M (ISI Kolkata — 1st Computer in India)1962 TIFRAC (1st Indigenous Computer) & 1986 Siddhartha (1st PC)C-DAC Pune (1988, Dr. Vijay Bhatkar): PARAM 8000 (1990/91), PARAM 10000 (1998), PARAM Padma (2002 — 1 Teraflop)

⚡ DEEP-DIVE:🔍 HEC-2M (1956) vs. TIFRAC (1962) vs. Siddhartha (1986) vs. PARAM 8000 (1991) →

HARDCODED CSS MATRIX 01 // INDIA'S PIONEERING COMPUTERS & C-DAC PARAM MILESTONES (1955–2002)

Chronological Evolution from HEC-2M (ISI Kolkata) & TIFRAC to PARAM Padma

1955–56 // ISI KOLKATAHEC-2M

Hollerith Electronic Digital Computer (imported from UK); 1st computer installed in India (at Indian Statistical Institute, Kolkata).

1960–62 // TIFR MUMBAITIFRAC

Named by PM J.L. Nehru; India’s 1st indigenously built general-purpose digital computer.

1986 // ECIL INDIASiddhartha

Developed by Electronics Corporation of India (ECIL); 1st general-purpose PC manufactured in India (installed at Bangalore Head Post Office).

1990–91 // C-DAC PUNEPARAM 8000

India’s 1st Supercomputer (1 GigaFLOPS), built by C-DAC under Dr. Vijay Bhatkar after US Cray denial.

1998 & 2002 // TERAFLOPPARAM 10000 & Padma

PARAM 10000 (100 GFLOPS, 1998) & PARAM Padma (2002 — 1 TeraFLOP; 1st Indian machine in Global Top-500).

I. The Architecture of Logic

Derived from the Latin root meaning 'to calculate', the modern computer is fundamentally a Data Processing Machine. It operates on a universal tripartite rhythm: receiving raw facts (Input), transmuting them through algorithmic instructions called a 'Programme' (Processing), and delivering structured meaning (Output Information).

The Alchemy of Information

II. The Sovereign Mainframe

While the world awoke to computation in the late 1940s, India’s digital heartbeat began in 1956. The HEC-2M (Hollerith Electronic Digital Computer), imported from British Tabulating Machine Works, was installed at the Indian Statistical Institute in Kolkata.

By 1962, dependency gave way to indigenous creation with TIFRAC (TATA Institute of Fundamental Research Automatic Calculator). However, the true crucible of Indian computing was born from geopolitical denial. When the US withheld Cray supercomputers in the 1980s, India established C-DAC in Pune (1988). This birthed the legendary PARAM series.

* PARAM 10000 achieved 100 Gigaflops in 1998. PARAM Padma became India's first to breach the global Top 500 (Rank 171, June 2003). Modern supercomputers boast immense storage and utilize thousands of processors to execute billions of instructions per second for complex scientific computations.

CH 02 · SUPERCOMPUTERS // I. Silicon Genesis, Supercomputing (PARAM) & Quantum Computing (Ch 01–03)CH 02 · NATIONAL SUPERCOMPUTING MISSION (NSM), AIRAWAT, PRATYUSH/MIHIR & GLOBAL TOP-500

The Sovereign Supercomputing Grid: NSM, PARAM Series, AIRAWAT & Global Exascale Titans

FLOPS Metric, C-DAC & IISc NSM Grid, AIRAWAT (C-DAC Pune), Pratyush & Mihir, Anupam (BARC), Floosolver (NAL) & El Capitan / Frontier

RADAR:Supercomputer Speed: Measured in FLOPS (PetaFLOPS = 10^15, ExaFLOPS = 10^18)Father of World Supercomputing: Seymour Cray (CDC 6600, 1964) | Father of Indian Supercomputing: Dr. Vijay Pandurang BhatkarIndia’s Fastest AI Supercomputer: AIRAWAT (Installed at C-DAC Pune) + PARAM Siddhi-AI, Pratyush (IITM Pune) & Mihir (NCMRWF Noida)Other Indian Series: ANUPAM (BARC Mumbai),ia-FLOOSOLVER (NAL Bengaluru), PACE (DRDO ANURAG), SAGA-220 (ISRO VSSC)Global Exascale Leaders (Top500): El Capitan (USA), Frontier (ORNL USA — 1st True Exascale), Aurora (USA), Fugaku (Japan), LUMI (Finland)

⚡ DEEP-DIVE:🔍 Matching PARAM, ANUPAM, PACE, Floosolver, SAGA-220 & AIRAWAT to Agencies →

I. National Supercomputing Mission (NSM) & Exascale Horizons

The Sovereign Supercomputing Grid: NSM, PARAM, AIRAWAT & Global Titans

FLOPS · C-DAC & IISc

Semantic CSS/SVG Diorama · The National Supercomputing Mission (NSM) Interconnect

Jointly Steered by MeitY & DST · Implemented by C-DAC (Pune) & IISc (Bengaluru) over NKN

Supercomputer / Series	Host Institute / Location	Architect / Nodal Agency & Significance
AIRAWAT PSAI	C-DAC, Pune	India’s largest and fastest AI Supercomputing system (13,170 TeraFLOPS / 13.17 PetaFLOPS sustained).
PARAM Siddhi-AI	C-DAC, Pune	High-performance computing-AI (HPC-AI) supercomputer commissioned under NSM (5.26 PetaFLOPS).
Pratyush & Mihir	IITM Pune & NCMRWF Noida	Dedicated to monsoon, weather forecasting & climate modelling (Ministry of Earth Sciences; replaced/upgraded by Arka & Arunika in 2024).
PARAM Pravega	IISc, Bengaluru	3.3 PetaFLOPS supercomputer installed under NSM at Indian Institute of Science.
PARAM Shivay · Shakti · Brahma · Ganga · Porul · Kamrupa	IIT BHU · IIT Kharagpur · IISER Pune · IIT Roorkee · NIT Trichy · IIT Guwahati	PARAM Shivay (IIT BHU, 2019) was the first supercomputer assembled indigenously under NSM, using the indigenous Rudra server board & Trinetra interconnect.
ANUPAM Series · PACE · FLOOSOLVER · SAGA-220	BARC (Mumbai) · DRDO (Hyderabad) · NAL (Bengaluru) · ISRO (VSSC)	ANUPAM = Bhabha Atomic Research Centre \| PACE = DRDO’s ANURAG lab \| Floosolver = NAL (1st Indian parallel computer, 1986) \| SAGA-220 = ISRO.

CH 03 · QUANTUM-CLASS // I. Silicon Genesis, Supercomputing (PARAM) & Quantum Computing (Ch 01–03)CH 03 · PARAM VIDYA, QUANTUM COMPUTING (QUBITS), FOUNDING PIONEERS & COMPUTER CLASSIFICATION

Quantum Horizons, Founding Pioneers of Computing & The Classification Matrix

PARAM Vidya & EKA, Superposition/Entanglement Qubits, Babbage/Lovelace/Turing/Von Neumann & Analog/Digital/Hybrid Taxonomy

RADAR:Quantum Computing: Qubits (0, 1, or Superposition of both), Entanglement; Google Sycamore, IBM Condor, India’s National Quantum Mission (NQM ₹6,003 Cr)Charles Babbage (1822 Difference Engine, 1837 Analytical Engine — Father of Computer) & Lady Ada Lovelace (World’s 1st Programmer)Alan Turing (Father of Modern Computer Science & AI — Turing Machine, 1936) & John von Neumann (1945 Stored-Program Architecture)By Mechanism: 1. Analog (Continuous physical quantities — Speedometer, Seismograph), 2. Digital (Binary 0/1), 3. Hybrid (ECG, ICU Machines, Petrol Pump)By Size/Power: Microcomputer (PC/Laptop/PDA) < Workstation < Minicomputer (PDP-8) < Mainframe (Banking/Railways) < Supercomputer

⚡ DEEP-DIVE:🔍 Babbage vs. Lovelace vs. Turing vs. Von Neumann vs. Kilby/Noyce vs. Hoff →

I. Quantum Computing (Qubits), Founding Pioneers & Classification

Quantum Horizons, Founding Fathers & Taxonomy of Computers

QUBIT · BABBAGE · TURING

1. Quantum Computing

Qubits & Superposition

Unlike classical bits constrained to $0$ or $1$ , a Quantum Bit (Qubit) leverages Superposition (existing in a linear combination of $|0 angle$ and $|1 angle$ simultaneously) and Quantum Entanglement. India launched the National Quantum Mission (NQM, 2023–31) with an outlay of ₹6,003.65 Crore to build 50–1000 physical qubit computers.

2. Classification by Mechanism

Analog, Digital & Hybrid

• Analog: Measures continuous physical quantities (pressure, temperature, voltage — e.g. Speedometer, Thermometer, Seismograph).
• Digital: Operates on discrete binary digits ( $0$ and $1$ — PCs, Smartphones).
• Hybrid: Combines analog measurement with digital processing (ECG/ICU hospital monitors, Radar, Automated Petrol Pumps).

3. Classification by Size

Micro to Supercomputer

• Microcomputer: Single-user microprocessor system (Desktop, Laptop, Tablet, Raspberry Pi).
• Minicomputer: Mid-sized multi-user system (DEC PDP-8, 1965 — 1st successful minicomputer).
• Mainframe: High-reliability bulk transaction server (IBM zSeries — Railways, Banking).

CH 04 · GENERATIONS-CPU // II. Five Generations, CPU Architecture, Memory Pyramid & Logic Gates (Ch 04–05, 09)CH 04 · THE FIVE GENERATIONS OF COMPUTERS (1940–PRESENT), VON NEUMANN CPU & I/O PERIPHERALS

The Five Generations of Hardware, Inside the CPU (ALU, CU, Registers) & Input/Output Peripherals

Vacuum Tubes → Transistors → ICs (Kilby/Noyce) → VLSI Microprocessors (Intel 4004) → ULSI/AI, Fetch-Decode-Execute Cycle & I/O Devices

RADAR:1st Gen (1940–56): Vacuum Tubes (ENIAC, EDVAC, UNIVAC-I; Machine Lang) | 2nd Gen (1956–63): Transistors (Bardeen, Brattain, Shockley; Assembly, FORTRAN/COBOL)3rd Gen (1964–71): Integrated Circuits (IC — Silicon chips by Jack Kilby & Robert Noyce) | 4th Gen (1971–Present): VLSI Microprocessors (1st: Intel 4004 in 1971 by Ted Hoff)5th Gen (Present & Beyond): ULSI (Ultra Large Scale Integration), Parallel Processing, Artificial Intelligence & QuantumCPU ("Brain of Computer"): 1. ALU (Arithmetic & Logic Ops), 2. Control Unit (CU — Nerve Centre / Timing Signals), 3. Registers (PC, IR, MAR, MDR, Accumulator)Input Devices: Keyboard (QWERTY — Christopher Sholes), Mouse (Douglas Engelbart, 1964), Scanner, MICR (Banking Cheques), OMR, OCR, Barcode, Light Pen, Joystick | Output: Monitor, Printer (Impact vs Non-Impact; DPI), Plotter

⚡ DEEP-DIVE:🔍 Instant Switching-Element & Language Matching Across Generations 1 to 5 →🔍 Program Counter (PC) vs. Instruction Register (IR) vs. MAR vs. MDR →🔍 Impact vs. Non-Impact Printers & MICR vs. OMR vs. OCR →

I. Hardware Evolution (1940–Present) & Von Neumann CPU

The Five Generations of Computers, CPU Architecture & Peripherals

ALU · CU · REGISTERS · I/O

Generation & Era	Core Switching Hardware	Memory & Speed	Software / Languages	Iconic Examples & Inventors
1st Gen (1940 – 1956)	Vacuum Tubes (Thermionic Valves — Lee De Forest / Ambrose Fleming)	Magnetic Drums & Punched Cards · Milliseconds ( $10^-3$ s)	Machine Language ( $0$ & $1$ ) · Batch Processing	ENIAC (1946 — Eckert & Mauchly), EDVAC, EDSAC (Wilkes), UNIVAC-I (1st commercial, 1951), IBM 650/701
2nd Gen (1956 – 1963)	Transistors (Invented 1947 at Bell Labs by Bardeen, Brattain & Shockley)	Magnetic Core & Magnetic Tape · Microseconds ( $10^-6$ s)	Assembly Language + Early HLLs (FORTRAN, COBOL)	IBM 1401, IBM 7090, CDC 1604, UNIVAC 1108, Honeywell 400
3rd Gen (1964 – 1971)	Integrated Circuits (ICs — SSI & MSI) on Silicon (Jack Kilby & Robert Noyce, 1958–59)	Large Magnetic Core & Disk · Nanoseconds ( $10^-9$ s)	Time-Sharing & Multiprogramming OS · BASIC, Pascal, C	IBM System/360, DEC PDP-8 & PDP-11, Honeywell 6000, CDC 6600
4th Gen (1971 – Present)	VLSI Microprocessors (1st Microprocessor: Intel 4004 in 1971 by Ted Hoff)	Semiconductor RAM (DRAM/SRAM) & Winchester HDD · Picoseconds ( $10^-12$ s)	GUI Operating Systems (Windows, macOS, UNIX) · C++, Java, SQL	Apple II, IBM PC (1981), Cray-1, Intel Pentium / Core Series
5th Gen (Present & Beyond)	ULSI (Ultra Large Scale Integration), Multi-Core, GPU & Quantum Processors	NVMe SSDs, Optical & Cloud Storage · Femtoseconds / GHz Parallel	Natural Language Processing (NLP), AI, Python, LISP, PROLOG	PARAM Siddhi-AI, IBM Watson, Quantum Systems, Robotics & Neural NPUs

1. Inside the CPU

ALU, Control Unit & Registers

• ALU (Arithmetic Logic Unit): Executes all mathematical ( $+,-, imes,\div$ ) and logical ( $extAND, OR, NOT, <, >$ ) operations.
• Control Unit (CU): Directs the flow of data via timing and control signals (Fetch → Decode → Execute → Store).
• Key Registers: Program Counter (PC) holds the address of the next instruction; Instruction Register (IR) holds the current instruction; MAR, MDR & Accumulator (AC).

2. Input Peripherals

Data Capture & Scanners

• Keyboard: 101–108 keys; Toggle Keys = Caps Lock, Num Lock, Scroll Lock; Modifier Keys = Shift, Ctrl, Alt.
• Direct Entry Scanners: MICR (Magnetic Ink Character Recognition — 9-digit code at bottom of bank cheques using iron-oxide ink), OMR (Optical Mark Reader — exam sheets), OCR (Optical Character Recognition), BCR (Barcode) & QR Code.

3. Output Peripherals

Monitors, Printers & Plotters

• Impact Printers (Strike ribbon against paper): Dot Matrix, Daisy Wheel, Line/Chain/Drum Printers.
• Non-Impact Printers (Quiet, faster, measured in PPM & DPI): Laser Printer (uses dry toner powder & photosensitive drum), Inkjet Printer (liquid ink nozzles), Thermal Printer (ATM/POS receipts).
• Plotter: Vector graphics output for CAD/blueprints.

CH 05 · MEMORY-STORAGE // II. Five Generations, CPU Architecture, Memory Pyramid & Logic Gates (Ch 04–05, 09)CH 05 · MEMORY HIERARCHY PYRAMID (REGISTERS, CACHE, RAM/ROM), OPTICAL/SSD STORAGE & BINARY UNITS

The Memory Pyramid: Primary (RAM/ROM/Cache) vs. Secondary Storage & Binary Capacity Ladder

SRAM vs. DRAM, ROM/PROM/EPROM/EEPROM, BIOS/CMOS, Magnetic/Optical (CD/DVD/Blu-Ray Lasers)/SSD Media & Bit-to-Geopbyte Table

RADAR:Speed Hierarchy (Fastest → Slowest): CPU Registers > Cache Memory (L1 > L2 > L3 — built from SRAM) > Main Memory (DRAM) > SSD (NVMe) > Magnetic HDD > Optical Disc > Magnetic TapeRAM (Volatile — Read/Write): SRAM (Flip-Flops / Transistors; fast, no refresh, used in Cache) vs. DRAM (Capacitors; slower, requires constant refreshing, used as Main RAM)ROM (Non-Volatile — Permanent Firmware/BIOS): PROM (One-time programmable), EPROM (Erased by UV light), EEPROM (Erased electrically — Flash Memory / Pen Drive / SSD)Optical Storage Laser Wavelengths: CD (700 MB — 780 nm Infrared) · DVD (4.7–17 GB — 650 nm Red Laser) · Blu-Ray Disc (25–50 GB — 405 nm Blue-Violet Laser) | Magnetic Tape = Sequential AccessMemory Units (1024 = 2^10): 4 Bits = 1 Nibble | 8 Bits = 1 Byte | KB → MB → GB → TB → PB (Peta) → EB (Exa) → ZB (Zetta) → YB (Yotta) → Brontobyte → Geopbyte (Highest!)

⚡ DEEP-DIVE:🔍 Why SRAM Is Used for Cache & Why DRAM Requires Constant Refreshing →🔍 Cold Boot vs. Warm Boot, POST, BIOS in ROM & Why Clock Time Persists →🔍 Bit, Nibble, Byte, Powers of 2 (2^10 to 2^80) & Word Length →

I. Primary vs. Secondary Memory & Binary Capacity Ladder

The Memory Pyramid: Cache, RAM/ROM, Optical Lasers & Storage Units

SRAM vs DRAM · ROM · 2¹⁰ UNITS

📐 SEMANTIC ASCII-CSS DIORAMA 01 // THE MEMORY HIERARCHY PYRAMID & BINARY CAPACITY LADDER SPEED & COST PER BIT INCREASE UPWARDS (▲) · CAPACITY INCREASES DOWNWARDS (▼)

     SPEED ▲               /\
     COST  |              /  \      1. CPU REGISTERS (<1 ns)
     UP    |             /────\
           |            / L1/L2\    2. CACHE MEMORY (SRAM)
           |           /────────\
           |          / MAIN RAM \  3. PRIMARY RAM (DRAM)
           |         /────────────\
           |        /  NVMe / SSD  \ 4. FLASH SOLID-STATE
           |       /────────────────\
     SIZE  ▼      / MAGNETIC HDD/TAPE\ 5. SECONDARY / TERTIARY
                 +--------------------+

     EXACT BINARY MEMORY CAPACITY LADDER (2¹⁰ = 1024):
     +---------------------------------------------------+
     | • 1 Bit = 0 or 1   | 4 Bits = 1 Nibble            |
     | • 8 Bits = 1 Byte  | 1024 Bytes = 1 Kilobyte (KB) |
     | • 1024 KB = 1 MB   | 1024 MB = 1 Gigabyte (GB)    |
     | • 1024 GB = 1 TB   | 1024 TB = 1 Petabyte (PB)    |
     | • 1024 PB = 1 EB   | 1024 EB = 1 Zettabyte (ZB)   |
     | • 1024 ZB = 1 YB (Yottabyte = 2⁸⁰ Bytes)          |
     | • 1024 YB = 1 Brontobyte → 1024 BB = 1 GEOPBYTE!  |
     +---------------------------------------------------+

1. Volatile Primary Memory

SRAM vs. DRAM & Cache

• SRAM (Static RAM): Built using 6-transistor flip-flops; retains data as long as power is supplied without needing refresh; extremely fast & expensive; used to build CPU Cache (L1, L2, L3).
• DRAM (Dynamic RAM): Stores each bit in a tiny capacitor that leaks charge and must be refreshed thousands of times per second; cheaper & denser; used as main system RAM (SDRAM, DDR4, DDR5).

2. Non-Volatile Firmware

ROM, PROM, EPROM & EEPROM

• ROM (Read-Only Memory): Stores permanent boot firmware (BIOS / UEFI) that executes the POST (Power-On Self-Test).
• PROM: Programmable once by user (fuses blown).
• EPROM: Erased by exposing quartz window to Ultraviolet (UV) light.
• EEPROM: Electrically Erasable Programmable ROM—erased byte-by-byte electrically (foundation of modern Flash Memory, Pen Drives & SSDs!).

3. Secondary & Optical Media

HDD, Optical Lasers & SSD

• Magnetic Disk (HDD): Concentric rings called Tracks divided into wedge-shaped Sectors.
• Optical Discs (Pits & Lands): CD-ROM = 700 MB (780 nm IR laser); DVD = 4.7 GB single-layer / 8.5 GB dual-layer (650 nm red laser); Blu-Ray (BD) = 25 GB single / 50 GB dual (405 nm blue-violet laser).

CH 06 · SOFTWARE-LANGS // III. Software, OS Kernel, Programming Languages, DBMS & Office Suite (Ch 06, 10)CH 06 · SYSTEM vs APPLICATION SOFTWARE, OPERATING SYSTEMS, TRANSLATORS & PROGRAMMING LANGUAGES

The Soul of the Machine: Operating Systems, Compilers vs. Interpreters & Programming Languages

BIOS/Booting (Cold vs Warm), OS Functions (Kernel, Paging, Thrashing, Deadlock), Assembler/Compiler/Interpreter & Creators of FORTRAN to Python

RADAR:System Software (OS, Device Drivers, BIOS, Utilities, Language Translators) vs. Application Software (Word Processors, Spreadsheets, DBMS, Browsers) | Open-Source: Linux, Android, Apache, Mozilla, PythonOperating System (OS): Manages CPU Scheduling, Memory (Virtual Memory, Paging, Swapping; Thrashing = excessive paging), File System & Deadlock (Banker’s Algorithm)UNIX (1969 — Ken Thompson & Dennis Ritchie at Bell Labs) · Linux (1991 — Linus Torvalds) · MS-DOS (1981 — CLI) · Windows (1985) · macOS/iOS · Android (Andy Rubin — Linux Kernel)Language Translators: 1. Assembler (Assembly → Machine Code), 2. Compiler (Translates WHOLE High-Level program at once — C, C++), 3. Interpreter (Translates LINE-BY-LINE — Python, BASIC, Ruby, JS)Language Creators: FORTRAN (1957 — John Backus, 1st HLL!) · LISP (1958 — John McCarthy, AI) · COBOL (1959 — Grace Hopper, Business) · BASIC (Kemeny & Kurtz) · C (1972 — Dennis Ritchie) · C++ (Bjarne Stroustrup) · Java (1995 — James Gosling) · Python (1991 — Guido van Rossum)

⚡ DEEP-DIVE:🔍 Execution Speed, Error Reporting & Hybrid Bytecode Languages (Java/Python) →🔍 Virtual Memory, Thrashing & Coffman’s 4 Necessary Conditions for Deadlock →

I. Operating Systems, Translators & Programming Languages

The Software Stack: OS Kernel, Compilers vs. Interpreters & Languages

KERNEL · COMPILER · HLL

HARDCODED CSS MATRIX 06 // THE THREE LANGUAGE TRANSLATORS & LINKER/LOADER PIPELINE

How Source Code Becomes Executable Machine Code ( $0$ and $1$ )

1. ASSEMBLERAssembly → Machine

Converts low-level Assembly mnemonics (MOV, ADD, SUB) into binary object code.

2. COMPILERWhole Program at Once

Scans the entire HLL source program at once, reports all syntax errors together, and generates standalone object code (e.g. C, C++, Go, Fortran).

3. INTERPRETERLine-by-Line Execution

Translates and executes HLL code statement by statement (line-by-line), stopping immediately at the first error (e.g. Python, Ruby, JavaScript, BASIC).

4. LINKER & LOADERLibrary Link → RAM

Linker combines object files & libraries into an executable (.exe); Loader loads the executable from disk into RAM for CPU execution.

Language & Year	Creator / Architect	Primary Domain & Exam Highlights
FORTRAN (1957)	John Backus & IBM	Formula Translation — World’s first High-Level Programming Language (HLL); built for scientific & numerical computing.
LISP (1958) & PROLOG (1972)	John McCarthy (LISP) · Alain Colmerauer (PROLOG)	List Processing & Programming in Logic — foundational languages of Artificial Intelligence (AI).
COBOL (1959)	Dr. Grace Murray Hopper (CODASYL)	Common Business-Oriented Language — designed for business, banking, and administrative data processing.
BASIC (1964) & Pascal (1970)	John Kemeny & Thomas Kurtz (BASIC) · Niklaus Wirth (Pascal)	Beginner's All-purpose Symbolic Instruction Code & structured teaching languages.
C (1972) & C++ (1983)	Dennis Ritchie (C at Bell Labs) · Bjarne Stroustrup (C++)	C was created to rewrite the UNIX OS kernel; C++ added Object-Oriented Programming (OOP: Classes, Inheritance, Polymorphism, Encapsulation).
Java (1995) · Python (1991) · JS (1995)	James Gosling (Java) · Guido van Rossum (Python) · Brendan Eich (JS)	Java uses both Compiler (to Bytecode) & JVM Interpreter ("Write Once, Run Anywhere"); Python dominates modern AI/Data Science.

CH 07 · NETWORKS-OSI // IV. Computer Networks, OSI/TCP-IP, Cybersecurity, AI & Silicon Lexicon (Ch 07–08, 11)CH 07 · COMPUTER NETWORKS (LAN/MAN/WAN), TOPOLOGIES, OSI 7-LAYER MODEL, HARDWARE & WEB PROTOCOLS

The Global Mesh: Network Topologies, The 7-Layer OSI Stack, Hardware & Internet Protocols

Simplex/Half/Full-Duplex, Bus/Star/Ring/Mesh Topologies, OSI Layers 1–7, Hub/Switch/Router/Gateway & IPv4 (32-Bit) vs. IPv6 (128-Bit)

RADAR:Transmission Modes: Simplex (Unidirectional — TV/Radio, Keyboard) · Half-Duplex (Walkie-Talkie) · Full-Duplex (Bidirectional simultaneous — Telephone) | PAN (Bluetooth) < LAN (Ethernet IEEE 802.3) < MAN < WAN (Internet; ARPANET 1969)Topologies: Bus (Single backbone + Terminators), Star (Central Hub/Switch), Ring (Token passing), Mesh (n(n-1)/2 links — Highest reliability!), Tree (Hierarchical)OSI 7-Layer Model (Bottom Layer 1 → Top Layer 7): 1. Physical (Bits — Hub, Repeater, Cables) → 2. Data Link (Frames, MAC Address 48-bit — Switch, Bridge, NIC) → 3. Network (Packets, IP Address — Router) → 4. Transport (Segments, TCP/UDP, Port Numbers) → 5. Session → 6. Presentation (Encryption/SSL, Compression, ASCII/JPEG) → 7. Application (HTTP, FTP, SMTP, DNS)IPv4 vs. IPv6: IPv4 = 32-bit (4 Octets in dotted decimal, e.g. 192.168.1.1; Loopback = 127.0.0.1) vs. IPv6 = 128-bit (8 groups of 4 Hex digits) | MAC Address = 48-bit (6 Bytes Hex burned into NIC ROM)Web Pioneers: Internet (Vint Cerf & Bob Kahn — TCP/IP) · World Wide Web (Tim Berners-Lee, 1989 CERN — HTML, HTTP, URL) · E-Mail (Ray Tomlinson, 1971 — @ symbol; Shiva Ayyadurai)

⚡ DEEP-DIVE:🔍 The Single Most Tested Networking Question in Competitive Exams →🔍 Classes A, B, C, D, E, Loopback (127.0.0.1) & IPv4 vs. IPv6 Bit Lengths →🔍 CC vs. BCC, SMTP vs. POP3 vs. IMAP & MIME →

I. Network Topologies, OSI 7-Layer Stack & Internet Protocols

The Global Mesh: OSI 7-Layer Architecture, Hardware & IPv4/IPv6

OSI 7 LAYERS · TCP/IP · ROUTER

🌐 SEMANTIC ASCII-CSS DIORAMA 02 // ISO-OSI 7-LAYER MODEL (DATA UNIT, PROTOCOLS & HARDWARE PER LAYER) MNEMONIC (1→7): "PLEASE DO NOT THROW SAUSAGE PIZZA AWAY"

     +---------------------------------------------------+
     | LYR | OSI LAYER    | PDU (UNIT) | DEVICES / PROTOS|
     +-----+--------------+------------+-----------------+
     |  7  | Application  | Data/Msg   | HTTP,FTP,SMTP,DNS
     |  6  | Presentation | Data       | SSL/TLS,JPEG,ASCII
     |  5  | Session      | Data       | NetBIOS, RPC    |
     |  4  | Transport    | SEGMENT    | TCP, UDP (Ports)|
     |  3  | Network      | PACKET     | ROUTER, IP, ICMP|
     |  2  | Data Link    | FRAME      | SWITCH,Bridge,MAC
     |  1  | Physical     | BIT (0/1)  | HUB,Repeater,Cat6
     +---------------------------------------------------+

     IPv4 vs. IPv6 vs. MAC ADDRESS (HIGH-YIELD COMPARISON)
     +---------------------------------------------------+
     | 1. IPv4 ADDRESS (Logical — Layer 3 Network):      |
     |    • 32-Bit (4 Bytes) in Dotted Decimal           |
     |    • Example: 192.168.1.1 (Each octet: 0 to 255)  |
     |    • Loopback (Self-Test) IP: 127.0.0.1           |
     +---------------------------------------------------+
     | 2. IPv6 ADDRESS (Logical — Layer 3 Network):      |
     |    • 128-Bit (16 Bytes) in 8 Hex Groups (Colon)   |
     +---------------------------------------------------+
     | 3. MAC ADDRESS (Physical/Hardware — Layer 2 NIC): |
     |    • 48-Bit (6 Bytes) in 6 Hex Pairs (00:1A:...)  |
     +---------------------------------------------------+

1. Network Topologies

Bus, Star, Ring & Mesh

• Bus: All nodes share a single coaxial/backbone cable with terminators at both ends.
• Star: All nodes connect to a central Hub or Switch (if the central switch fails, the whole network goes down).
• Mesh: Every node connects directly to every other node; requires $racn(n-1)2$ bidirectional links for $n$ nodes (most fault-tolerant!).

2. Networking Hardware

Hub vs. Switch vs. Router

• Repeater & Hub (Layer 1): Repeater regenerates weak signals; Hub broadcasts data blindly to all ports.
• Bridge & Switch (Layer 2): Intelligent device that forwards frames to the exact destination port using MAC Addresses.
• Router (Layer 3): Routes packets across different networks using IP Addresses.
• Gateway: Connects two completely dissimilar protocol networks.

3. E-Mail & Web Protocols

SMTP, POP3, IMAP & DNS

• SMTP (Simple Mail Transfer Protocol): Used strictly for sending / pushing outgoing emails.
• POP3 & IMAP: Used for receiving / retrieving emails from a mail server (IMAP syncs across multiple devices).
• DNS (Domain Name System): Phonebook of the Internet—translates domain names (google.com) into IP addresses.
• DHCP: Automatically assigns IP addresses to hosts.

CH 08 · CYBER-AI-CLOUD // IV. Computer Networks, OSI/TCP-IP, Cybersecurity, AI & Silicon Lexicon (Ch 07–08, 11)CH 08 · SOFTWARE BUGS, CYBERSECURITY & MALWARE, CRYPTOGRAPHY, CLOUD COMPUTING & ARTIFICIAL INTELLIGENCE

The Sentinel & The Neural Mind: Bugs, Malware, Cybersecurity, Cloud Computing & AI

Grace Hopper’s 1947 Moth Bug, Virus vs. Worm vs. Trojan vs. Ransomware, Firewalls, IT Act 2000, Cloud (IaaS/PaaS/SaaS) & AI/ML/LLMs

RADAR:Software Errors: Bug (Error in code — 1st actual moth bug found by Grace Hopper in Harvard Mark II, 1947), Debugging (Fixing bugs), Patch (Software fix), Glitch (Minor hardware/software fault)Malware Taxonomy: 1. Virus (Needs host file + human action to spread; 1st PC Virus: "Brain" 1986; 1st Network Virus: "Creeper" 1971), 2. Worm (Self-replicating standalone over network — NO host file needed! e.g. Stuxnet, ILOVEYOU), 3. Trojan Horse (Disguised as legitimate software; does NOT self-replicate; creates Backdoor), 4. Ransomware (Encrypts files — WannaCry, Locky, Petya), 5. Spyware/Keylogger (Pegasus)Cyber Attacks & Defense: Phishing (Fake emails/sites), Spoofing, DoS/DDoS, Man-in-the-Middle, SQL Injection, Zero-Day Exploit | Firewall (Hardware/Software packet filter), Proxy Server, VPN, SSL/TLS (HTTPS), Cookies (Session state stored on client browser)Indian Cyber Law: Information Technology (IT) Act, 2000 (Enacted 17 Oct 2000; Amended 2008) · CERT-In (2004 — National Nodal Agency for Cyber Incident Response)Emerging Tech: Cloud Models — IaaS (Infra), PaaS (Platform), SaaS (Software) | AI (Coined by John McCarthy, 1956 Dartmouth; IBM Deep Blue beat Kasparov 1997; AlphaGo; Generative AI Transformers)

⚡ DEEP-DIVE:🔍 Self-Replication vs. Host Requirement & Famous Malware Examples →🔍 Symmetric (AES) vs. Asymmetric (RSA Public/Private Keys) & HTTPS →

I. Software Bugs, Malware, Cybersecurity, Cloud & AI

The Sentinel & The Neural Mind: Bugs, Malware, Cyber Law & AI

MALWARE · IT ACT 2000 · CLOUD · AI

1. Errors, Bugs & Glitches

1947 Mark II Moth & Bugs

• The First "Bug" (9 Sept 1947): Rear Admiral Grace Hopper and her team taped an actual moth trapped in Relay #70 of the Harvard Mark II computer into the logbook: "First actual case of bug being found."
• Syntax Error: Violation of grammar rules (caught by Compiler).
• Logical Error: Program runs without crashing but produces wrong output.
• Runtime Error: Crash during execution (e.g. division by zero).

2. Cloud Computing Stack

IaaS vs. PaaS vs. SaaS

• IaaS (Infrastructure as a Service): Virtual machines, storage & networking (AWS EC2, Google Compute Engine, Cloudflare R2).
• PaaS (Platform as a Service): Managed runtime & deployment environment for developers (Google App Engine, Heroku).
• SaaS (Software as a Service): Ready-to-use end-user cloud apps in a browser (Gmail, Google Docs, Microsoft 365).

3. Web Evolution & AI

Web 1.0 → 2.0 → 3.0 & AI

• Web 1.0 (1990s): Static Read-Only HTML pages.
• Web 2.0 (2004+): Read-Write interactive Social Web & user-generated content.
• Web 3.0: Decentralized Semantic Web powered by Blockchain (Satoshi Nakamoto, 2008) & Smart Contracts.
• AI: Coined by John McCarthy (1956 Dartmouth Conference).

CH 09 · BINARY-GATES // II. Five Generations, CPU Architecture, Memory Pyramid & Logic Gates (Ch 04–05, 09)CH 09 · NUMBER SYSTEMS (BINARY, OCTAL, DECIMAL, HEX), COMPLEMENTS, ASCII/UNICODE & BOOLEAN LOGIC GATES

The Algebra of Silicon: Number Systems, Binary Conversions, Character Codes & Logic Gates

Base-2/8/10/16 Conversions, 1’s & 2’s Complement, BCD/EBCDIC/ASCII/Unicode & Universal Gates (NAND & NOR)

RADAR:4 Number Systems: Binary (Base 2: 0,1) · Octal (Base 8: 0–7; 1 Octal digit = 3 Binary bits) · Decimal (Base 10: 0–9) · Hexadecimal (Base 16: 0–9, A–F where A=10..F=15; 1 Hex digit = 4 Binary bits / 1 Nibble)Signed Binary Representation: 1’s Complement (Invert all bits: 0↔1) & 2’s Complement (1’s Complement + 1; used by modern ALUs for subtraction!)Character Encoding Standards: BCD (4-bit) · ASCII (7-bit = 128 chars; Extended ASCII = 8-bit = 256 chars; A=65, a=97, 0=48) · EBCDIC (8-bit used in IBM Mainframes) · ISCII (8-bit Indian scripts) · Unicode (UTF-8 / UTF-16 / UTF-32)Boolean Algebra (George Boole, 1854) & Logic Gates: Basic Gates = AND (Y = A·B), OR (Y = A+B), NOT (Inverter: Y = Ā)Universal Gates (Can build ANY logic circuit alone!): 1. NAND Gate (NOT + AND) & 2. NOR Gate (NOT + OR) | Exclusive Gates: XOR (1 when inputs differ) & XNOR (Equivalence Gate: 1 when inputs match)

⚡ DEEP-DIVE:🔍 Fast Step-by-Step Binary ↔ Decimal ↔ Octal ↔ Hexadecimal Rules →🔍 Universal Gates (NAND/NOR), De Morgan’s Laws & XOR Parity Checker →

I. Positional Number Systems, Complements & Boolean Logic Gates

Binary, Octal, Decimal, Hexadecimal & Universal Logic Gates

BASE 2·8·10·16 · NAND & NOR

🔢 SEMANTIC ASCII-CSS DIORAMA 03 // THE 7 BOOLEAN LOGIC GATES TRUTH TABLE & UNIVERSAL GATES UNIVERSAL GATES = NAND & NOR · EXCLUSIVE GATES = XOR & XNOR

     2-INPUT LOGIC GATES TRUTH TABLE SUMMARY:
     +---------------------------------------------------+
     | A  B | AND(A·B) | OR(A+B) | NAND | NOR | XOR |XNOR|
     +------+----------+---------+------+-----+-----+----+
     | 0  0 |    0     |    0    |  1   |  1  |  0  | 1  |
     | 0  1 |    0     |    1    |  1   |  0  |  1  | 0  |
     | 1  0 |    0     |    1    |  1   |  0  |  1  | 0  |
     | 1  1 |    1     |    1    |  0   |  0  |  0  | 1  |
     +---------------------------------------------------+
     ★ NAND & NOR are called UNIVERSAL GATES because any
       Boolean function (AND, OR, NOT) can be built using
       ONLY NAND gates or ONLY NOR gates!

     RADIX / BASE CONVERSION CHEAT-SHEET:
     +---------------------------------------------------+
     | • Binary (Base 2):      Digits {0, 1}             |
     | • Octal (Base 8):       Digits {0..7} (3 Bits/dig)|
     | • Decimal (Base 10):    Digits {0..9}             |
     | • Hexadecimal (Base 16):Digits {0..9, A=10..F=15} |
     |                         (4 Bits / 1 Nibble per dig|
     +---------------------------------------------------+
     | QUICK EQUIVALENTS:                                |
     | • (10)₁₀ = (1010)₂ = (12)₈ = (A)₁₆               |
     | • (15)₁₀ = (1111)₂ = (17)₈ = (F)₁₆               |
     | • (255)₁₀ = (11111111)₂ = (377)₈ = (FF)₁₆        |
     +---------------------------------------------------+

CH 10 · DBMS-OFFICE // III. Software, OS Kernel, Programming Languages, DBMS & Office Suite (Ch 06, 10)CH 10 · DATABASE MANAGEMENT SYSTEMS (RDBMS, KEYS, SQL), MS OFFICE SUITE & MASTER KEYBOARD SHORTCUTS

Relational Databases (RDBMS & SQL), MS Office Suite (Word, Excel, PowerPoint) & Keyboard Shortcuts

E.F. Codd’s RDBMS, Primary/Foreign/Candidate Keys, SQL Sub-Languages (DDL/DML/DCL/TCL), Excel Formulas & High-Yield Shortcuts

RADAR:DBMS & RDBMS (E.F. Codd, 1970): Tuple = Row (Record) | Attribute = Column (Field) | Cardinality = Number of Rows | Degree = Number of Columns!Database Keys: Super Key (Uniquely identifies row) → Candidate Key (Minimal Super Key) → Primary Key (Chosen Candidate Key: Unique + NOT NULL) → Alternate Key (Unchosen Candidate Keys) → Foreign Key (Links two tables — Referential Integrity)SQL 4 Sub-Languages: 1. DDL (Data Definition: CREATE, ALTER, DROP, TRUNCATE), 2. DML (Data Manipulation: SELECT, INSERT, UPDATE, DELETE), 3. DCL (Control: GRANT, REVOKE), 4. TCL (Transaction: COMMIT, ROLLBACK, SAVEPOINT) | ACID: Atomicity, Consistency, Isolation, DurabilityMS Word & PowerPoint: Word Zoom (10% to 500%; Default Font/Size: Calibri 11pt; Portrait Page; Thesaurus = Shift+F7; Spell Check = F7; Font Dialog = Ctrl+D; Hyperlink = Ctrl+K; Justify = Ctrl+J) | PowerPoint Zoom (10% to 400%; Start Slide Show = F5; From Current Slide = Shift+F5; New Slide = Ctrl+M)MS Excel: Zoom (10% to 400%) | Formula always starts with "=" | Cell Reference: Relative (A1) vs Absolute (

A

⚡ DEEP-DIVE:🔍 Primary Key vs. Candidate Key vs. Foreign Key & DELETE vs. TRUNCATE vs. DROP →🔍 Minimum & Maximum Zoom Percentages, Default Fonts & File Extensions →🔍 Complete Function Key Action Table Across Windows, Browsers & MS Office →

I. Relational Databases (RDBMS), SQL & MS Office Productivity Suite

RDBMS Keys, SQL Commands & Master MS Office Keyboard Shortcuts

SQL · EXCEL · SHORTCUTS

1. RDBMS & SQL Sub-Languages

DDL, DML, DCL & TCL

• DDL (Data Definition — Schema): CREATE, ALTER, DROP, TRUNCATE, RENAME.
• DML (Data Manipulation — Rows): SELECT, INSERT, UPDATE, DELETE.
• DCL (Data Control — Permissions): GRANT, REVOKE.
• TCL (Transaction Control): COMMIT, ROLLBACK, SAVEPOINT.
• Degree vs. Cardinality: Degree = Number of Columns (Attributes); Cardinality = Number of Rows (Tuples)!

2. MS Word & PowerPoint

High-Frequency Shortcuts

• Alignment: Left (Ctrl+L), Center (Ctrl+E), Right (Ctrl+R), Justify (Ctrl+J).
• Formatting: Superscript $X^2$ (Ctrl+Shift++), Subscript $H_2O$ (Ctrl+=), Font Dialog (Ctrl+D), Clear Formatting (Ctrl+Space).
• Tools: Spell Check (F7), Thesaurus (Shift+F7), Hyperlink (Ctrl+K), Page Break (Ctrl+Enter).
• PowerPoint: New Slide (Ctrl+M), Duplicate Slide (Ctrl+D), Start Show (F5), From Current Slide (Shift+F5).

3. MS Excel Formulas & Keys

Cells, Errors & Functions

• Cell Address: Column Letter + Row Number (e.g. A1; Absolute reference = $A$ 1 via F4).
• Shortcuts: Edit Active Cell (F2), AutoSum (Alt + =), Insert New Worksheet (Shift + F11), Current Date (Ctrl + ;), Current Time (Ctrl + Shift + :).
• Excel Errors: ##### (Column too narrow), #DIV/0! (Divide by zero), #NAME? (Typo in function name), #VALUE! (Wrong argument type), #REF! (Invalid cell reference).

CH 11 · LEXICON-PORTS // IV. Computer Networks, OSI/TCP-IP, Cybersecurity, AI & Silicon Lexicon (Ch 07–08, 11)CH 11 · THE MASTER SILICON LEXICON: 100+ COMPUTER FULL FORMS, TCP/UDP PORTS & FILE EXTENSIONS

The Silicon Lexicon: High-Yield Computer Acronyms, Network Port Numbers & File Extensions

Complete Exam Reference of Hardware/Software/Network Full Forms, Standard Well-Known Ports & Document/Media File Formats

RADAR:Well-Known TCP/UDP Port Numbers: FTP = 20 (Data) & 21 (Control) · SSH = 22 · Telnet = 23 · SMTP = 25 · DNS = 53 · DHCP = 67/68 · HTTP = 80 · POP3 = 110 · IMAP = 143 · HTTPS (SSL/TLS) = 443Hardware & Memory Full Forms: BIOS (Basic Input Output System) · CMOS (Complementary Metal-Oxide Semiconductor) · SMPS (Switched-Mode Power Supply) · UPS (Uninterruptible Power Supply) · USB (Universal Serial Bus — Ajay Bhatt) · HDMI (High-Definition Multimedia Interface) · NVMe (Non-Volatile Memory Express)Web & Network Full Forms: HTTP (HyperText Transfer Protocol) · URL (Uniform Resource Locator) · HTML (HyperText Markup Language) · CSS · JSON · XML · AJAX · MIME (Multipurpose Internet Mail Extensions) · VoIP (Voice over IP) · Wi-Fi (Wireless Fidelity — IEEE 802.11) · Li-Fi (Light Fidelity)File Extensions: .docx/.xlsx/.pptx (MS Office XML, 2007+) · .pdf (Portable Document Format) · .exe/.bat/.apk (Executable) · .jpg/.png/.gif/.svg/.webp (Images; GIF/PNG support transparency; SVG = Vector) · .mp3/.wav/.flac (Audio) · .mp4/.mkv/.avi (Video) · .zip/.rar/.tar (Archive)

⚡ DEEP-DIVE:🔍 Twisted Pair (Cat6 RJ-45) vs. Coaxial vs. Fiber Optic (Total Internal Reflection) →🔍 Ethernet (802.3), Wi-Fi (802.11), Bluetooth (802.15.1) & Generation Speeds →🔍 Founders & Launch Years of Google, Microsoft, Apple, WWW, Linux & Wikipedia →

I. Master Silicon Lexicon: Full Forms, Ports & Extensions

High-Yield Computer Acronyms, TCP/UDP Ports & File Formats

A–Z ACRONYMS · PORTS

Acronym	Exact Full Form	Acronym	Exact Full Form
ASCII	American Standard Code for Information Interchange	BIOS	Basic Input/Output System
CMOS	Complementary Metal-Oxide Semiconductor	COBOL	Common Business-Oriented Language
DBMS	Database Management System	DHCP	Dynamic Host Configuration Protocol
DNS	Domain Name System	EEPROM	Electrically Erasable Programmable Read-Only Memory
ENIAC	Electronic Numerical Integrator and Computer	FAT / NTFS	File Allocation Table / New Technology File System
FIFO / LIFO	First-In First-Out (Queue) / Last-In First-Out (Stack)	FLOPS	Floating-Point Operations Per Second
FORTRAN	Formula Translation	FTP / SMTP	File Transfer Protocol / Simple Mail Transfer Protocol
GUI / CLI	Graphical User Interface / Command Line Interface	HDMI	High-Definition Multimedia Interface
HTTP / HTTPS	HyperText Transfer Protocol (Secure)	ICMP / IGMP	Internet Control / Group Message Protocol
IMAP / POP3	Internet Message Access Protocol / Post Office Protocol v3	MAC / NIC	Media Access Control / Network Interface Card
MICR / OCR	Magnetic Ink / Optical Character Recognition	MODEM	Modulator – Demodulator
MPEG / JPEG	Moving Picture / Joint Photographic Experts Group	POST	Power-On Self-Test
RAID	Redundant Array of Independent Disks	SMPS / UPS	Switched-Mode Power Supply / Uninterruptible Power Supply
SQL	Structured Query Language	URL / URI	Uniform Resource Locator / Identifier
USB	Universal Serial Bus (Co-invented by Ajay Bhatt)	VIRUS	Vital Information Resources Under Siege

DD 01 // INDIA’S FIRST COMPUTERS ↩ Back to Chapter

HEC-2M (1956) vs. TIFRAC (1962) vs. Siddhartha (1986) vs. PARAM 8000 (1991)

• 1st Computer Installed in India: HEC-2M (1955–56 at Indian Statistical Institute, Kolkata).
• 1st Indigenously Designed Computer in India: TIFRAC (1960–62 at TIFR Mumbai, named by PM J.L. Nehru).
• 1st General-Purpose PC Made in India: Siddhartha (built by ECIL; installed at Main Post Office, Bengaluru on 16 Aug 1986).
• 1st Supercomputer of India: PARAM 8000 (1990–91, C-DAC Pune under Dr. Vijay Bhatkar).

DD 02 // INDIAN SUPERCOMPUTING LABS ↩ Back to Chapter

Matching PARAM, ANUPAM, PACE, Floosolver, SAGA-220 & AIRAWAT to Agencies

• PARAM & AIRAWAT: C-DAC (Pune)
• ANUPAM Series: BARC (Bhabha Atomic Research Centre, Mumbai)
• PACE (Processor for Aerodynamic Computation and Evaluation): ANURAG Lab of DRDO (Hyderabad)
• Floosolver (1986): NAL (National Aerospace Laboratories, Bengaluru)
• SAGA-220: ISRO (Vikram Sarabhai Space Centre, Thiruvananthapuram)
• Pratyush, Mihir, Arka & Arunika: IITM Pune & NCMRWF Noida (Weather/Climate).

DD 03 // PIONEERS OF COMPUTING ↩ Back to Chapter

Babbage vs. Lovelace vs. Turing vs. Von Neumann vs. Kilby/Noyce vs. Hoff

• Charles Babbage: Father of the Computer (Difference Engine 1822, Analytical Engine 1837).
• Lady Ada Lovelace: World’s First Computer Programmer.
• Alan Turing: Father of Modern Computer Science & AI (Universal Turing Machine 1936, Bombe codebreaker, Turing Test 1950).
• John von Neumann: Stored-Program Architecture (data and instructions stored together in the same memory!).
• Jack Kilby & Robert Noyce: Invented the Integrated Circuit (IC, 1958–59).
• Marcian "Ted" Hoff: Designed the world’s first commercial microprocessor, the 4-bit Intel 4004 (1971).

DD 04 // THE 5 GENERATIONS HARDWARE ↩ Back to Chapter

Instant Switching-Element & Language Matching Across Generations 1 to 5

• 1st Gen (1940–56): Vacuum Tubes + Magnetic Drums + Machine/Binary Language (ENIAC, UNIVAC-I).
• 2nd Gen (1956–63): Transistors + Magnetic Core + Assembly, FORTRAN, COBOL (IBM 1401).
• 3rd Gen (1964–71): Integrated Circuits (ICs) + Time-Sharing OS (IBM 360, PDP-8).
• 4th Gen (1971–Present): VLSI Microprocessors + Semiconductor RAM + GUI OS.
• 5th Gen (Present+): ULSI + Parallel Processing + AI / Quantum.

DD 05 // CPU REGISTERS & BUSES ↩ Back to Chapter

Program Counter (PC) vs. Instruction Register (IR) vs. MAR vs. MDR

• Program Counter (PC): Holds the memory address of the NEXT instruction to be fetched.
• Instruction Register (IR): Holds the CURRENT instruction being decoded/executed.
• Memory Address Register (MAR): Holds the memory address to be read from or written to.
• Memory Data/Buffer Register (MDR/MBR): Holds the actual data fetched from or sent to memory.
• System Buses: Address Bus is unidirectional (CPU → Memory/IO), whereas Data Bus is bidirectional!

DD 06 // PRINTERS & SCANNERS TRAP ↩ Back to Chapter

Impact vs. Non-Impact Printers & MICR vs. OMR vs. OCR

• Impact Printers (Noisy, strike ribbon, can print carbon copies): Dot Matrix (measured in CPS), Daisy Wheel, Line/Drum/Chain Printers.
• Non-Impact Printers (Quiet, cannot print carbon copies; speed in PPM, resolution in DPI): Laser Printer (dry toner + drum), Inkjet Printer (liquid ink), Thermal Printer (heat-sensitive paper in ATMs).
• MICR (9-Digit Code on Cheques): Digits 1–3 = City (aligned with PIN) · Digits 4–6 = Bank · Digits 7–9 = Branch.

DD 07 // SRAM vs. DRAM & CACHE ↩ Back to Chapter

Why SRAM Is Used for Cache & Why DRAM Requires Constant Refreshing

• SRAM (Static RAM): Uses 6 transistors (flip-flop) per bit; does NOT need refreshing; ultra-fast (1–3 ns), expensive, low density → used for CPU Cache (L1, L2, L3).
• DRAM (Dynamic RAM): Uses 1 transistor + 1 capacitor per bit; capacitor leaks charge so it must be refreshed every few milliseconds; slower, cheaper, high density → used for Main System RAM.

DD 08 // ROM, BIOS, CMOS & BOOTING ↩ Back to Chapter

Cold Boot vs. Warm Boot, POST, BIOS in ROM & Why Clock Time Persists

• BIOS (in Non-Volatile ROM/Flash): Runs POST (Power-On Self-Test) to check hardware, then loads the OS bootloader (MBR/GPT) from disk into RAM.
• CMOS Chip (Powered by CR2032 Coin Battery): Stores user BIOS settings and the Real-Time System Clock (RTC) so date/time stay accurate even when the PC is unplugged!
• Cold Boot (Hard Boot): Starting a computer from a completely powered-off state.
• Warm Boot (Soft Boot): Restarting an already running computer (Ctrl + Alt + Del).

DD 09 // BINARY CAPACITY CONVERSIONS ↩ Back to Chapter

Bit, Nibble, Byte, Powers of 2 (2^10 to 2^80) & Word Length

• Power-of-2 Ladder (in Bytes):
•

1 KB = 2^10 B = 1024 B

•

1 MB = 2^20 B

1 GB = 2^30 B

1 TB = 2^40 B

•

1 PB = 2^50 B

1 EB = 2^60 B

1 ZB = 2^70 B

1 YB = 2^80 B

.
• Half Byte:

4 Bits = 1 Nibble = 1 Hexadecimal digit

DD 10 // COMPILER vs. INTERPRETER ↩ Back to Chapter

Execution Speed, Error Reporting & Hybrid Bytecode Languages (Java/Python)

• Compiler: Translates the entire high-level program into machine code at once before execution; generates an object/executable file; faster execution; reports all syntax errors together (C, C++).
• Interpreter: Translates and executes high-level code line-by-line; no separate object file saved; halts immediately at the first error (BASIC, Ruby, JavaScript).

DD 11 // OS KERNEL, DEADLOCK & PAGING ↩ Back to Chapter

Virtual Memory, Thrashing & Coffman’s 4 Necessary Conditions for Deadlock

• Virtual Memory & Paging: Allows a system to run programs larger than physical RAM by swapping fixed-size blocks (Pages) between RAM (Frames) and disk (Swap/Pagefile).
• Thrashing: When the OS spends more time swapping pages in and out of disk than executing actual instructions (high page-fault rate).
• 4 Conditions for Deadlock: 1. Mutual Exclusion, 2. Hold and Wait, 3. No Preemption, 4. Circular Wait.

DD 12 // OSI 7-LAYER DEVICE & PDU MAP ↩ Back to Chapter

The Single Most Tested Networking Question in Competitive Exams

• Layer 1 (Physical — Bits): Hub, Repeater, Modem, Cables (RJ-45, Fiber Optic).
• Layer 2 (Data Link — Frames / MAC Address): Switch, Bridge, NIC (ARP maps IP → MAC).
• Layer 3 (Network — Packets / IP Address): Router, Layer-3 Switch, IP, ICMP (ping), IPSec.
• Layer 4 (Transport — Segments / Port Numbers): TCP (Connection-oriented, reliable) vs. UDP (Connectionless, fast streaming/DNS).
• Layers 5–7 (Session, Presentation, Application — Data): Gateway, Firewall, Proxy, HTTP, FTP, SMTP, DNS.

DD 13 // IPv4 CLASSES & PRIVATE IPs ↩ Back to Chapter

Classes A, B, C, D, E, Loopback (127.0.0.1) & IPv4 vs. IPv6 Bit Lengths

• IPv4 Classes (by 1st Octet):
• Class A: 1 to 126 (Large networks; Default Mask 255.0.0.0)
• 127.x.x.x: Reserved for Loopback / Localhost testing (127.0.0.1)!
• Class B: 128 to 191 (Medium networks; Mask 255.255.0.0)
• Class C: 192 to 223 (Small LANs; Mask 255.255.255.0)
• Class D: 224 to 239 (Multicasting) · Class E: 240 to 255 (Research/Experimental).

DD 14 // E-MAIL FIELDS & PROTOCOLS ↩ Back to Chapter

CC vs. BCC, SMTP vs. POP3 vs. IMAP & MIME

• CC (Carbon Copy): All recipients can see every other recipient’s email address.
• BCC (Blind Carbon Copy): Recipients in BCC are invisible to other recipients.
• SMTP (Port 25/587): Pushes/sends email from client to server and between mail servers.
• POP3 (Port 110): Downloads email to a single device and typically deletes it from the server.
• IMAP (Port 143/993): Syncs emails on the server across multiple devices.

DD 15 // VIRUS vs. WORM vs. TROJAN ↩ Back to Chapter

Self-Replication vs. Host Requirement & Famous Malware Examples

• Does it Self-Replicate?
• Worm: YES (automatically over networks without human action or host file!).
• Virus: YES (but requires a host file/program and human action to trigger).
• Trojan Horse: NO! (Masquerades as legitimate software to trick the user into installing it, opening a backdoor).

DD 16 // ENCRYPTION, SSL/TLS & FIREWALL ↩ Back to Chapter

Symmetric (AES) vs. Asymmetric (RSA Public/Private Keys) & HTTPS

• Symmetric Encryption: Uses the SAME secret key to encrypt and decrypt (e.g. AES, DES — fast, used for bulk data).
• Asymmetric (Public-Key) Encryption: Uses a Public Key to encrypt and a mathematically linked Private Key to decrypt (e.g. RSA, ECC — used in SSL/TLS handshakes and Digital Signatures).

DD 17 // NUMBER SYSTEM CONVERSIONS ↩ Back to Chapter

Fast Step-by-Step Binary ↔ Decimal ↔ Octal ↔ Hexadecimal Rules

• Binary to Octal: Group binary bits in threes ( $2^3=8$ ) from right to left.
• Binary to Hexadecimal: Group binary bits in fours ( $2^4=16$ ) from right to left.
• 2’s Complement of a Binary Number: Invert all bits (1’s complement) and add

1

to the Least Significant Bit (LSB); OR shortcut: copy bits from right to left up to and including the first

1

, then invert all remaining bits to the left!

DD 18 // BOOLEAN ALGEBRA & DE MORGAN ↩ Back to Chapter

Universal Gates (NAND/NOR), De Morgan’s Laws & XOR Parity Checker

• De Morgan’s Two Theorems:
1.

NOT(A \cdot B) = NOT(A) + NOT(B)

(NAND = Bubbled OR)
2.

NOT(A + B) = NOT(A) \cdot NOT(B)

(NOR = Bubbled AND).
• Minimum NAND Gates Needed: 1 for NOT, 2 for AND, 3 for OR, 4 for XOR.

DD 19 // RDBMS KEYS & NORMALIZATION ↩ Back to Chapter

Primary Key vs. Candidate Key vs. Foreign Key & DELETE vs. TRUNCATE vs. DROP

• DELETE vs. TRUNCATE vs. DROP (SQL Trap):
• DELETE (DML): Deletes specific rows using a WHERE clause; can be rolled back.
• TRUNCATE (DDL): Removes all rows from a table instantly, but keeps the table structure/schema intact.
• DROP (DDL): Completely deletes both the rows AND the table structure from the database!

DD 20 // MS WORD, EXCEL & PPT LIMITS ↩ Back to Chapter

Minimum & Maximum Zoom Percentages, Default Fonts & File Extensions

• Zoom Range Comparison (Repeated SSC/Bank Question!):
• MS Word: Minimum = 10% · Default = 100% · Maximum = 500%!
• MS Excel: Minimum = 10% · Default = 100% · Maximum = 400%!
• MS PowerPoint: Minimum = 10% · Default = 100% · Maximum = 400%!
• Font Size Dropdown in Word: Shows 8 pt to 72 pt (Manual typing allows 1 pt to 1638 pt!).

DD 21 // FUNCTION KEYS (F1 TO F12) ↩ Back to Chapter

Complete Function Key Action Table Across Windows, Browsers & MS Office

• F1: Universal Help · F2: Rename file/folder OR Edit active cell in Excel · F3: Search · F4: Repeat last action / Toggle $A$ 1 in Excel / Alt+F4 closes active window · F5: Refresh / Reload / Start PPT Slide Show / Go To in Word · F7: Spell & Grammar Check (Shift+F7 = Thesaurus) · F11: Toggle Full-Screen in Browsers (Shift+F11 = New Excel Sheet) · F12: Save As dialog box in MS Office!

DD 22 // TRANSMISSION MEDIA & CABLES ↩ Back to Chapter

Twisted Pair (Cat6 RJ-45) vs. Coaxial vs. Fiber Optic (Total Internal Reflection)

• Guided (Wired) Media:
1. Twisted Pair Cable (UTP/STP): Uses RJ-45 (8-pin) connector for Ethernet LANs (RJ-11 is 4/6-pin for telephones).
2. Coaxial Cable: Uses BNC connector (Cable TV).
3. Optical Fiber Cable: Transmits data as light pulses using the principle of Total Internal Reflection (TIR); immune to electromagnetic interference (EMI) and fastest long-distance medium.

DD 23 // IEEE 802 STANDARDS & WIRELESS ↩ Back to Chapter

Ethernet (802.3), Wi-Fi (802.11), Bluetooth (802.15.1) & Generation Speeds

• IEEE 802 LAN/MAN Standards:
• IEEE 802.3: Ethernet (CSMA/CD)
• IEEE 802.11: Wi-Fi Wireless LAN (CSMA/CA)
• IEEE 802.15.1: Bluetooth WPAN (Invented by Jaap Haartsen at Ericsson, 1994; named after Danish King Harald Bluetooth).

DD 24 // SOCIAL MEDIA, TECH FOUNDERS & YEARS ↩ Back to Chapter

Founders & Launch Years of Google, Microsoft, Apple, WWW, Linux & Wikipedia

• Microsoft (1975): Bill Gates & Paul Allen · Apple (1976): Steve Jobs, Steve Wozniak & Ronald Wayne · WWW (1989): Tim Berners-Lee · Linux (1991): Linus Torvalds · Amazon (1994): Jeff Bezos · Google (1998): Larry Page & Sergey Brin · Wikipedia (2001): Jimmy Wales & Larry Sanger · Facebook (2004): Mark Zuckerberg · YouTube (2005): Jawed Karim, Steve Chen, Chad Hurley · Twitter/X (2006): Jack Dorsey et al. · WhatsApp (2009): Jan Koum & Brian Acton.