ASKiIMAN™ REALM 02 / COMPUTING
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The Silicon Machine

Architecture, Processing, Memory & The Physical Computer

Central Doctrine

How does a computer's physical architecture transform abstract instructions and data into actual computation? Moving past the history of calculation, this realm dissects the modern digital computer. We map the flow of electricity through the Central Processing Unit, the hierarchy of volatile and non-volatile memory, and the intricate bus systems that bind hardware into a functional whole.

CPU → ALU → CONTROL → REGISTERS → MEMORY → STORAGE → BUSES → ARCHITECTURE

The Internal Chambers

Ontology of Computer Hardware

CHAMBER 01

The Computer as Machine

IN
→
CPUMEM
→
OUT
  • Architecture vs. Organization
  • Functional units (Processing, Memory, I/O, Control)
  • Interconnection and data movement
  • Instructions and data pathways
CHAMBER 02

The CPU

  • The Central Processing Unit and Cores
  • Single-core vs. Multi-core processors
  • ALU, Control Unit, and internal Registers
  • Instruction execution and data processing
CHAMBER 03

The ALU

  • Arithmetic Logic Unit operations
  • Addition, Subtraction, Multiplication, Division
  • Logical ops (AND, OR, NOT, XOR) and Comparisons
  • Bitwise shifts and ALU inputs/outputs
CHAMBER 04

The Control Unit

  • Instruction control and sequencing
  • Memory read/write and ALU control signals
  • Coordination of CPU components
  • Hardwired vs. Microprogrammed control
CHAMBER 05

Registers

  • High-speed temporary storage
  • General-purpose vs. Special-purpose
  • Program Counter (PC) & Instruction Register (IR)
  • Why registers are faster than main memory
CHAMBER 06

The Bus System

  • Data bus, Address bus, Control bus
  • Bus width and data transfer capacity
  • Bus arbitration and shared vs. point-to-point
  • Processor-memory & I/O communication
CHAMBER 07

The Instruction

ADD
R1, R2
  • Machine instruction format and length
  • Opcode (Operation code) and Operand
  • Source/Destination operands & Immediate data
  • Machine language and instruction encoding
CHAMBER 08

Fetch-Decode-Execute

F
D
E
  • The CPU instruction cycle
  • Memory access and Write-back
  • Updating the Program Counter
  • Basic instruction pipeline concept
CHAMBER 09

Instruction Set Arch

SOFTWARE
  • ISA: The Hardware/Software boundary
  • Data movement, Arithmetic, Logical, Control-flow
  • Load, Store, Add, Jump, Call, Return
  • RISC vs. CISC abstraction models
CHAMBER 10

CPU Clock & Timing

  • Clock signal, cycle, and frequency (MHz/GHz)
  • Instruction timing and CPI (Cycles Per Instruction)
  • Synchronization and timing signals
  • Why frequency vs. performance is not 1:1
CHAMBER 11

Memory Workspace

00
01
A4
03
04
05
06
FF
  • Primary/Main memory (RAM) locations
  • Addresses, Bytes, and Words
  • Read/Write operations and access time
  • Volatile vs. Non-volatile memory
CHAMBER 12

RAM

  • Random Access Memory mechanics
  • DRAM (Dynamic) vs. SRAM (Static)
  • Volatile storage cells and speed limits
  • DIMMs, memory modules, and CPU relation
CHAMBER 13

ROM & Non-Volatile

  • Read Only Memory (ROM, PROM, EEPROM)
  • Flash memory and firmware storage
  • Retaining data without electrical power
  • Modern uses of flash memory
CHAMBER 14

Cache Memory

CPU
  • L1, L2, L3 cache hierarchy
  • Locality of reference (Temporal & Spatial)
  • Cache hit, cache miss, and hit ratio
  • Bridging the speed gap between CPU and RAM
CHAMBER 15

The Memory Hierarchy

REG
CACHE
RAM
STORAGE
  • Registers → Cache → RAM → SSD → HDD
  • Trade-offs: Speed vs. Capacity vs. Cost
  • HIGHER SPEED = SMALLER = HIGHER COST
CHAMBER 16

Secondary Storage

  • HDD (Magnetic platters, tracks, sectors, heads)
  • SSD (NAND flash storage and controllers)
  • Internal vs. External / Removable storage
  • Mechanical lag vs. Solid-state speed
CHAMBER 17

Storage Technologies

  • Magnetic, Optical, and Semiconductor storage
  • CDs, DVDs, Blu-ray, USB drives
  • Storage capacity units and reliability
  • The necessity of backup and redundancy
CHAMBER 18

Input / Output

⌨️
→
→
  • Input: Keyboard, Mouse, Scanner, Sensors
  • Output: Monitor, Printer, Speaker, Actuators
  • I/O controllers and peripheral devices
  • Communication between CPU and peripherals
CHAMBER 19

The Motherboard

  • CPU socket, memory slots, expansion slots
  • The Chipset and system interconnection
  • Storage, USB, display, and network interfaces
  • Firmware / BIOS / UEFI layer
CHAMBER 20

Specialized Computing

  • CPU (General-purpose) vs. GPU (Parallel)
  • Hardware Accelerators (DSP, NPU for AI)
  • System-on-Chip (SoC) integration
  • Handling complex graphics and neural networks
CHAMBER 21

Parallel Processing

  • Sequential vs. Parallel execution
  • Multicore CPUs and SIMD concepts
  • Data parallelism vs. Task parallelism
  • Performance gains and the limits of concurrency
CHAMBER 22

Interrupts & Exceptions

⚡
  • Hardware/Software interrupts and priorities
  • Interrupt Request (IRQ) and Service Routine (ISR)
  • Exceptions, faults, and traps
  • Why active polling is inefficient compared to interrupts
CHAMBER 23

DMA & I/O Transfer

I/O
CPU
MEM
  • Direct Memory Access controller
  • Bypassing the CPU for memory-to-device transfers
  • Programmed I/O vs. Interrupt-driven I/O
  • Enabling high-speed data flow
CHAMBER 24

System Performance

  • Instruction rate, IPC, and cache performance
  • Memory latency and bandwidth
  • I/O bottlenecks (The funnel effect)
  • Benchmarking and realistic measurement
CHAMBER 25

Power & Thermal

⚙️
  • Electrical power consumption and heat generation
  • Heat sinks, fans, and liquid cooling
  • Thermal throttling and power management
  • Performance vs. Power constraints
CHAMBER 26

Architecture Models

CPU
↔
MEM
INSTR
↔
CPU
↔
DATA
  • Von Neumann: Shared memory for instructions/data
  • The Von Neumann bottleneck
  • Harvard Architecture: Separate memory paths
  • Architectural trade-offs in modern design
CHAMBER 27

Word Size & Data Path

  • Bit width (8-bit, 16-bit, 32-bit, 64-bit)
  • Register width and Address width
  • Data path capacity and processor word size
  • Effect on addressing space and math precision
CHAMBER 28

Addressing

0x4F
→
DATA
  • Memory address space and addressable locations
  • Physical vs. Virtual addressing (Introduction)
  • Direct, indirect, immediate, and indexed modes
CHAMBER 29

Hardware Abstraction

OS
ISA
CHIP
PHYSICS
  • Transistor → Logic Circuit → Processor
  • ISA as the core interface layer
  • Why software abstracts physical transistor states
CHAMBER 30

Evolution to System

  • Transistor → Logic Gates → Digital Circuits
  • Registers → ALU + Control Unit = CPU
  • CPU + Memory + Motherboard = Computer
  • System-level integration
CHAMBER 31

Lexicon

  • CPU, ALU, Control Unit, Registers
  • Cache, RAM, ROM, HDD, SSD, Bus
  • Opcode, Operand, ISA, RISC, CISC
  • Interrupt, DMA, GPU, NPU, SoC
CHAMBER 32

Key Comparisons

  • CPU vs GPU | Single-core vs Multi-core
  • RAM vs ROM | SRAM vs DRAM
  • Cache vs RAM | Primary vs Secondary
  • RISC vs CISC | Von Neumann vs Harvard
CHAMBER 33

Complete Machine Map

I/O
BUS
CPU
CACHE
RAM
STORE
  • User → Input Device → I/O Controller
  • System Bus → CPU (CU, ALU, Registers)
  • Cache → RAM → Storage → Output
FINAL CHAMBER

The Bridge to Binary

REALM 02 explained the physical machine.
CPU → MEMORY → BUSES
↓
REALM 03 asks: How does it represent info?
01000010 01001001 01010100 01010011
Proceed to REALM 03 → THE BINARY UNIVERSE