Ontological Layer: Temporal Optimization
Pipelining & Performance
Making the Processor Work Faster by Overlapping Time
The Factory of Instructions
A processor does not become faster merely by rushing. True performance is achieved through the industrialization of time. By dividing instruction execution into discrete stages—Fetch, Decode, Execute, Memory, Writeback—the CPU transforms into an assembly line. Pipelining does not make an individual instruction complete faster; it overlaps the work of *many* instructions so that the aggregate throughput skyrockets. Realm 09 explores this beautiful choreography, the Hazards that disrupt it, and the mathematical formulas governing architectural efficiency.
The 12 Stages of Execution
Ontological Mapping: From Pipeline Overlap to Out-of-Order Execution
The Nature of Performance
- Execution time as the ultimate metric
- Instruction Count (Compiler dependency)
- Cycles Per Instruction (Architecture)
- Clock Rate (Hardware physical limit)
Clock & Cycle Time
- Clock frequency (MHz, GHz)
- Clock period duration
- Synchronizing functional units
- Frequency vs Actual Performance
Instruction Pipelining
- The assembly line analogy
- Overlapping independent operations
- Increasing aggregate throughput
- Pipeline fill and drain phases
Stages & Timing
- IF: Fetch from PC
- ID: Decode & read registers
- EX: ALU operations
- MEM: Data memory access
- WB: Register write-back
Structural Hazards
- Hardware resource conflicts
- Unified memory (IF & MEM collision)
- Resolved by resource duplication
- Split I-Cache and D-Cache
Data Hazards
- RAW, WAR, WAW dependencies
- Subsequent instr needs unwritten result
- Data Forwarding (Bypassing)
- Routing EX result directly to next EX
Control Hazards
- Branches disrupt the PC sequence
- Next instruction is unknown until EX
- Static vs Dynamic Branch Prediction
- Misprediction penalty (Flushes)
Stalls & Bubbles
- Load-Use dependencies
- Injecting NOPs (Bubbles)
- Deliberately idling stages
- Severe impact on overall CPI
Performance Math
- Ideal Pipeline CPI ≈ 1.0
- Actual CPI = Ideal CPI + Stall CPI
- Amdahl's Law limit on optimization
- Pipeline Speedup = T_seq / T_pipe
Superscalar Execution
- Multiple instructions issued per clock
- Instruction-Level Parallelism (ILP)
- Multiple execution units (ALU/FPU)
- Pushing CPI below 1.0 (IPC > 1)
Out-of-Order Execution
- Reordering instructions to avoid stalls
- Register Renaming (eliminating WAW/WAR)
- Speculative Execution past branches
- Reorder Buffer (ROB) for in-order retire
12 — Pipeline Engineering Laboratory
Pipelining and Superscalar design push a single processor to its absolute physical limits. When instruction-level parallelism runs dry and clock speeds hit the thermal wall, computer architects must look elsewhere for performance. They stop making a single processor faster, and start building systems with *many* processors. This brings us to Realm 10: Parallel Computing.