Ontological Layer: The Mathematics of Execution
DSP Fundamentals
Where Numbers Become Signals and Algorithms Become Systems
The Digital Engine
We have captured reality as an array of discrete numbers in Realm 07. Now, we must compute. Realm 08 forms the structural core of Digital Signal Processing. Here, abstract mathematical difference equations are physically realized using just three atomic components: Delays (memory), Multipliers (scaling), and Adders (accumulation). We build Direct-Form structures, explore the discrete-time Fourier transform (DTFT) on the unit circle, and evaluate the fierce computational cost of real-time execution.
The 14 Computational Nodes
Ontological Mapping: From Sequences to Structures
What Is DSP?
- Processing signals mathematically
- Digital vs Analog processing
- Programmability & Precision
- Perfect repeatability
Processing Chain
- Analog World → Anti-Alias Filter
- ADC → Discrete Sequences
- DSP Operations & Algorithms
- DAC → Reconstruction Filter → Analog
Sequence Operations
- Addition & Subtraction of sequences
- Multiplication & Scaling
- Delay, Advance, Time Reversal
- Accumulation and Differencing
Unit Delay (z⁻¹)
- The central memory operator
- Shifting samples in time: x[n-1]
- Hardware equivalent: Registers
- Building blocks of Delay Lines
MAC Operation
- Multiply And Accumulate (MAC)
- Applying coefficient weights (h_k)
- Summing results over time
- The core hardware execution unit of DSPs
Difference Equations
- Mathematical model of a digital filter
- Input/Output relationships in time
- Feedforward terms (b_k)
- Feedback/Recursive terms (a_k)
FIR vs IIR Bridges
- FIR: Finite Impulse Response (No feedback)
- IIR: Infinite Impulse Response (Feedback)
- Stability guarantees (FIR inherently stable)
- Conceptual foundation for Realm 09
DTFT Definition
- Discrete-Time Fourier Transform
- X(e^{jω}) = Σ x[n]e^{-jωn}
- Evaluates Z-transform on the Unit Circle
- Spectrum is always periodic in ω (2π)
System Realization
- Converting H(z) equations into structures
- Mapping to adders, multipliers, delays
- Signal flow graphs and block diagrams
- Hardware or software blueprinting
Direct Forms
- Direct Form I: Separate delay lines (Memory heavy)
- Direct Form II: Shared delay line (Canonical)
- Minimizing required memory elements
- Susceptibility to numerical overflow
Cascade & Parallel
- Cascade: Systems in series, H(z) = H1(z)·H2(z)
- Parallel: Systems in parallel, H(z) = H1(z)+H2(z)
- Reduces sensitivity to coefficient quantization
- Better numerical stability than high-order Direct Forms
Computational Cost
- Operations per sample (Complexity)
- Memory/storage requirements
- Latency vs Throughput in real-time
- Fixed-point vs Floating-point precision
DSP Classification
- Hardware vs Software realization
- Real-time processing vs Offline batch
- Recursive (IIR) vs Nonrecursive (FIR)
- Causal vs Noncausal implementation limits
14 — The DSP Engine Laboratory
You have successfully transformed pure math into computational architecture. By wiring delays, multipliers, and adders together, we can compute any difference equation on a stream of digital samples. But what equations should we compute? How do we choose the coefficients `h[n]` to filter out noise or isolate a specific frequency? You are now ready for Realm 09: Digital Filters.