f = 1/T / T_min ≥ t_cq + t_comb + t_su
SETUP: VALID_BEFORE / HOLD: VALID_AFTER
ARCHITECTURE: MASTER-SLAVE
STATE: RACE_PREVENTED
ASKiIMAN™ DOOR 03 / THE DIGITAL MACHINE / REALM 13
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Ontological Layer: The Synchronization of State

Timing & Race Conditions

The Heartbeat and Rhythm of the Digital Machine

The Dimension of Time

A digital circuit is not just about logical correctness; it must be correct in time. The clock signal orchestrates the flow of data, dividing chaos into discrete, predictable events. But signals take time to propagate. If data arrives too late (Setup violation), leaves too early (Hold violation), or loops uncontrollably (Race condition), the machine’s memory shatters. Realm 13 explores how we tame these physical constraints using edge-triggering and Master-Slave architectures.

CLOCK PERIOD → TIMING EVENT → SETUP / HOLD WINDOW → PROPAGATION DELAY → RACE CONDITION → MASTER-SLAVE ISOLATION → EDGE TRIGGERING

The 18 Timing Nodes

Ontological Mapping: From Delay to Synchronization

GROUP 01

Time in Systems

  • Continuous vs discrete time
  • Signal transitions
  • State-update intervals
  • Physical constraints on speed
 GROUP 02

Clock Signals

  • The oscillator heartbeat
  • Square wave idealization
  • Rising (Positive) Edge
  • Falling (Negative) Edge
 GROUP 03

Frequency & Period

  • Clock Period (T) in seconds
  • Frequency (f = 1/T) in Hz
  • Duty cycle representation
  • Speed vs power trade-offs
 GROUP 04

Propagation Delay

IN
OUT
  • Time from input to output change
  • Combinational logic delay (t_comb)
  • Physical transistor limits
  • Accumulation in deep circuits
 GROUP 05

Rise & Fall Time

  • Non-ideal signal transitions
  • Rise time (10% to 90%)
  • Fall time (90% to 10%)
  • Impact on edge-detection
 GROUP 06

Setup Time

  • Data stability requirement
  • Arrival BEFORE the clock edge
  • t_su specifications
  • Violations cause metastability
 GROUP 07

Hold Time

  • Data stability requirement
  • Holding AFTER the clock edge
  • t_h specifications
  • Preventing premature transitions
 GROUP 08

Clock-to-Q Delay

CLK
Q
  • Flip-flop internal response time
  • Time from Clock edge to Q output
  • t_cq specification
  • Drives the next combinational stage
 GROUP 09

Timing Relationships

  • The combined valid window
  • Data transition vs Clock edge
  • Interplay of delays and clocks
  • Ensuring reliable sampling
 GROUP 10

Race Conditions

  • Unintended sequential loops
  • Timing-dependent logic errors
  • Signals "racing" through gates
  • Unpredictable final states
 GROUP 11

Race-Around Condition

  • Specific to Level-Sensitive JK-FF
  • Occurs when J=1, K=1 (Toggle)
  • t_pulse > t_propagation
  • Continuous toggling during High clock
 GROUP 12

Master-Slave Solution

  • Two-stage isolation architecture
  • Master active on High (Captures)
  • Slave active on Low (Outputs)
  • Breaks the continuous feedback loop
 GROUP 13

Edge Triggering

  • Sampling only at exact transitions
  • Positive (Rising) Edge
  • Negative (Falling) Edge
  • Eliminates level-sensitive transparency
 GROUP 14

Timing Diagrams

CLK
D
Q
  • Visualizing signals over time
  • Multi-waveform synchronization
  • Identifying edge triggers
  • Analyzing sequential behavior
 GROUP 15

Clock Skew

  • Spatial clock arrival differences
  • Physical wire routing delays
  • Reduces effective valid window
  • Can cause hold-time violations
 GROUP 16

Synchronization

  • Crossing clock domains
  • Asynchronous inputs
  • 2-FF Synchronizer chains
  • Mitigating metastability
 GROUP 17

Timing Constraints

  • Max frequency determination
  • T_min ≥ t_cq + t_comb_max + t_su
  • Hold constraint: t_comb_min ≥ t_h - t_cq
  • Critical Path analysis
 FINAL PROTOCOL

18 — Timing & Verification Laboratory

Given: t_cq = 2ns, t_su = 1ns, t_h = 0.5ns
Path A delay = 4ns, Path B delay = 7ns
T_min = 2 + 7 + 1 = 10ns => f_max = 100MHz
[1] TRACE WAVEFORMS [2] CHECK VIOLATIONS [3] CALC FREQUENCY [4] IDENTIFY RACE [5] ADD SYNCHRONIZER

A circuit that works perfectly on paper will fail in reality if timing is ignored. By understanding setup, hold, propagation delays, and race conditions, we secure the foundation. We are now ready to string these perfectly timed memory elements together in Realm 14: Registers.

SIMULATION RUNNING