Q(t+1) = f(Q(t), X)
CLOCK: ACTIVE_RISING_EDGE
FEEDBACK: LOOP_CLOSED
STATE: MEMORY_ACTIVE
ASKiIMAN™ DOOR 03 / THE DIGITAL MACHINE / REALM 11
--:-- · -- --- ----

Ontological Layer: State & Time Dependence

Sequential Logic

The Introduction of Memory and Feedback

The Machine Acquires a Past

Up to this point, the digital machine has lived entirely in the present; its outputs dictated solely by current inputs. Realm 11 introduces the profound concept of Feedback. By routing an output back into the input, the circuit gains Memory. Its next decision is no longer purely combinational; it depends on what it remembers. Governed by the heartbeat of a Clock, the machine steps through discrete, predictable States.

INPUTS → COMBINATIONAL LOGIC → NEXT STATE Q(t+1) → MEMORY ELEMENT → CLOCK EVENT → FEEDBACK LOOP → PRESENT STATE Q(t) → STATE TRANSITION

The 17 Sequential Nodes

Ontological Mapping: Nodes 01 - 17

GROUP 01

Fundamental Concept

  • 01.1 Sequential Circuit Logic
  • 01.2 Logic with Memory
  • 01.4 Previous State influence
  • 01.5 Contrast with Combinational
 GROUP 02

Memory Concept

  • 02.1 Information Storage
  • 02.2 The State Variable
  • 02.3 Stored Binary Information
  • 02.4 Feedback-based Storage
 GROUP 03

Feedback Principle

  • 03.1 Output fed back to input
  • 03.2 The Feedback Loop
  • 03.3 Stable Logic States
  • 03.4 State Retention Mechanism
 GROUP 04-05

Current vs Next State

  • 04.1 Present Stored State Q(t)
  • 04.2 State Variables & Vectors
  • 05.1 State Transition Concept
  • 05.4 Next-State Function Q(t+1)
 GROUP 06, 13

State Transitions

  • 06.3 Transition Conditions (Inputs)
  • 13.1 States (Circles/Nodes)
  • 13.2 Directed Transitions (Arrows)
  • 13.5 Diagram ↔ Table Conversion
 GROUP 07

Clock Dependence

  • 07.1 The Clock Signal Generator
  • 07.3 System Synchronization
  • 07.4 Active Clock Edges
  • 07.5 Rising vs 07.6 Falling Edge
 GROUP 08-09

Sync vs Async Logic

  • 08.1 Common Clock Requirement
  • 08.2 State Update Predictability
  • 09.2 Input-Triggered State Changes
  • 09.4 Asynchronous Stability Issues
 GROUP 10

Sequential Structure

  • 10.1 Combinational Logic Section
  • 10.2 Memory Elements Block
  • 10.3 The Feedback Path
  • 10.4 Inputs → State → Outputs
 GROUP 11-12

State Equations & Tables

INQ(t)Q(t+1)
0S0S0
1S0S1
XS1S0
  • 11.1 Next-State Boolean Equations
  • 12.1 Present-State Column
  • 12.2 Input vs 12.3 Next-State Mapping
  • 12.5 State-Table Construction
 GROUP 14

Memory Elements

[ LATCHES ]
↓
[ FLIP-FLOPS ]
↓
[ REGISTERS ]
  • 14.1 Latches (Level-Sensitive)
  • 14.2 Flip-flops (Edge-Triggered)
  • 14.3 Registers (Multi-bit Storage)
  • Bridge to Realm 12: Latches & FFs
 GROUP 15

System Timing

  • 15.1 Clock Period (T) & Frequency (f)
  • 15.3 Propagation Delay in Memory
  • 15.4 State-Update Instant
  • Setup & Hold Time Concepts
 FINAL PROTOCOL

16-17 — Sequential Design Laboratory

1. IDENTIFY STATE VARIABLES
2. DERIVE NEXT-STATE EQUATIONS
3. CONSTRUCT STATE TRANSITION TABLE
[1] ANALYZE LOGIC [2] MAP FEEDBACK [3] DRAW DIAGRAM [4] VERIFY TIMING [5] IMPLEMENT FSM

This realm introduces the fundamental abstraction of Time into the Digital Machine. By understanding how Present State and Input merge to dictate the Next State, we are perfectly prepared for Realm 12, where we study the physical hardware (Latches & Flip-Flops) that makes this memory possible.

SIMULATION RUNNING