ARCHITECTURE: ISLAND_STYLE / CLB_MATRIX
LUT: 2^N_SRAM_CELLS / MUX_SELECT
HARDWARE_AS_SOFTWARE
STATE: RECONFIGURABLE
ASKiIMAN™ DOOR 03 / THE DIGITAL MACHINE / REALM 21
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Ontological Layer: Metamorphic Hardware

Programmable Logic

Soft Silicon and Reconfigurable Arrays

Hardware That Behaves Like Software

For 20 Realms, we built circuits permanently etched into silicon. Here, the paradigm shatters. By utilizing grids of programmable fuses, LUTs, and dynamic switch matrices, we create a blank canvas of hardware. From early PLAs and PALs to the massive parallel processing power of modern FPGAs, the Digital Machine achieves the ability to physically restructure its own logic gates in milliseconds via a simple bitstream.

HARDWIRED ASIC → ROM LOGIC → PLA / PAL → MACROCELLS (CPLD) → LOOK-UP TABLES (LUT) → FPGA GRID → SWITCH MATRIX → BITSTREAM CONFIGURATION

The 12 Configuration Nodes

Ontological Mapping: From Fuses to FPGAs

GROUP 01

Fixed vs Programmable

STATIC
VS
DYNAMIC
  • ASIC (Application-Specific IC)
  • High NRE costs / Custom masks
  • PLD (Programmable Logic Device)
  • Off-the-shelf reconfigurability
 GROUP 02

ROM as Combinational Logic

  • Address lines = Logic Inputs
  • Data outputs = Logic Outputs
  • Fixed AND array (Decoder)
  • Programmable OR array (Memory)
 GROUP 03

PLA Architecture

  • Programmable Logic Array
  • Programmable AND plane
  • Programmable OR plane
  • Highly flexible, slower speed
 GROUP 04

PAL Architecture

  • Programmable Array Logic
  • Programmable AND plane
  • Fixed (Hardwired) OR plane
  • Faster, simpler, less flexible
 GROUP 05

Macrocells & GAL

  • Generic Array Logic (GAL)
  • Output Logic Macrocell (OLMC)
  • Optional D-Flip-Flop bypass
  • Programmable output polarity
 GROUP 06

CPLD Overview

  • Complex Programmable Logic Device
  • Coarse-grained architecture
  • Multiple PAL-like blocks
  • Programmable Interconnect Array (PIA)
 GROUP 07

FPGA Architecture

  • Field-Programmable Gate Array
  • Fine-grained "Island" style
  • Configurable Logic Blocks (CLBs)
  • I/O Blocks (IOBs) at periphery
 GROUP 08

Look-Up Tables (LUTs)

  • The core of FPGA computation
  • Truth table stored in SRAM
  • N inputs = 2^N SRAM cells
  • Implemented via Multiplexers
 GROUP 09

Routing Resources

  • Global and local routing nets
  • Switch Matrices (turn corners)
  • Connection Boxes (CLB to wire)
  • Pass transistors & multiplexers
 GROUP 10

Programming Technologies

  • SRAM (Volatile, re-programmable)
  • Flash (Non-volatile, re-programmable)
  • Antifuse (Non-volatile, OTP)
  • Radiation hardness considerations
 GROUP 11

Bitstream Configuration

  • The .bit / configuration file
  • JTAG, SPI, or Parallel loading
  • Power-on boot sequence (SRAM)
  • Setting LUTs and Switch Matrices
 FINAL PROTOCOL

12 — Soft Hardware Laboratory

1. WRITE RTL (VERILOG/VHDL)
2. SYNTHESIZE TO LUTs + FFs
3. PLACE & ROUTE (SWITCH MATRIX)
4. GENERATE BITSTREAM
[1] SELECT ARCHITECTURE [2] MAP TO LUTS [3] ROUTE SIGNALS [4] TIMING CLOSURE [5] FLASH CHIP

FPGAs represent the ultimate evolution of digital logic design. You are no longer constrained by the physical gates soldered to a board; you command the silicon itself to reconfigure its internal structure based on your HDL code. The Digital Machine has become fluid.

HARDWARE RECONFIGURING...