PDP = P_D × t_pd
FAN_OUT_MAX = I_OH / I_IH
CMOS_I_STATIC ≈ 0
TTL_I_DRIVE: HIGH
ASKiIMAN™ DOOR 03 / THE DIGITAL MACHINE / REALM 19
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Ontological Layer: Physical IC Technology

Logic Families

Speed, Power, and Electrical Compatibility

The Physics of Computation

Earlier realms defined what logic a circuit should perform. This realm asks: Can the physical integrated circuits actually communicate that logic reliably and fast enough? By exploring the BJT-based TTL family and the MOS-based CMOS family, we confront the engineering realities of propagation delay, power dissipation, fan-out limits, and the complexities of interfacing different electrical worlds.

DIGITAL LOGIC → PHYSICAL IC → LOGIC FAMILY → VOLTAGE / CURRENT → SPEED / POWER → FAN-OUT & DELAY → INTERFACING

The 20 Hardware Nodes

Ontological Mapping: TTL vs CMOS Dynamics

GROUP 01-02

IC Characteristics

  • Logic Family Concept
  • Voltage Levels (VIH, VIL, VOH, VOL)
  • Switching / Speed characteristics
  • Power Dissipation parameters
 GROUP 03

Fan-Out & Drive

  • Output current sourcing/sinking
  • Max number of connected inputs
  • I_OH / I_IH calculation
  • Loading effects on voltage
 GROUP 04

Propagation Delay

IN
OUT
  • Time from input to output change
  • t_pLH (Low to High) vs t_pHL
  • Rise and Fall delay effects
  • System speed limitations
 GROUP 05

Power Dissipation

  • Static (Quiescent) Power
  • Dynamic (Switching) Power
  • P = C * V² * f relationship
  • Thermal management impact
 GROUP 06

Noise Immunity

  • Noise Margin HIGH (V_OH - V_IH)
  • Noise Margin LOW (V_IL - V_OL)
  • Tolerance to stray voltages
  • Preventing false switching
 GROUP 07-09

TTL (Transistor-Transistor)

  • BJT-based current steering
  • Standard 74xx series characteristics
  • High power consumption (Static)
  • Schottky variants for speed (74LS)
 GROUP 10-12

CMOS (Complementary MOS)

  • PMOS + NMOS complementary pairs
  • Near-zero static power draw
  • High input impedance (Voltage drive)
  • Dynamic power proportional to freq
 GROUP 13

TTL vs CMOS

  • Current vs Voltage controlled
  • Speed vs Power optimization
  • Fan-out capabilities comparison
  • Noise margin superiority (CMOS)
 GROUP 14-16

Interfacing Families

  • Voltage level mismatches (V_OH to V_IH)
  • TTL to CMOS: Pull-up resistors needed
  • CMOS to TTL: Current sink limitations
  • Buffer and Driver IC applications
 GROUP 17

Open-Collector / Drain

  • Output stage without active pull-up
  • Requires external pull-up resistor
  • Allows "Wired-AND" logic sharing
  • Interfacing different voltage levels
 GROUP 18

Tri-State Logic

  • Logic 0, Logic 1, and High-Z
  • High-Impedance disconnected state
  • Output Enable (OE) control pin
  • Essential for shared data buses
 GROUP 19

Speed-Power Product

  • PDP (Power-Delay Product) metric
  • Faster switching = higher power
  • Heat dissipation constraints
  • Selecting optimal logic sub-families
 FINAL PROTOCOL

20 — Hardware Interface Laboratory

Fan-out = min(I_OH/I_IH, I_OL/I_IL)
NM_H = V_OH(min) - V_IH(min)
P_dyn = C_L * V_DD² * f
[1] CALCULATE FAN-OUT [2] CHECK VOLTAGE COMPATIBILITY [3] ADD PULL-UPS [4] MEASURE DELAY [5] ESTIMATE POWER

A logically perfect circuit will fail if the physical voltages do not match. By understanding how CMOS and TTL behave under load, you bridge the gap between theoretical logic diagrams and physical PCB implementation. We are now ready for Realm 20: Digital System Design.

SIMULATION RUNNING