MOD = 2^N / MAX_COUNT = MOD - 1
SYNC: PARALLEL / RIPPLE: SERIAL
ARCHITECTURE: SEQUENTIAL
STATE: COUNTING
ASKiIMAN™ DOOR 03 / THE DIGITAL MACHINE / REALM 15
--:-- · -- --- ----
MSB
BIT 2
BIT 1
LSB

Ontological Layer: Sequential Progression

Counters

Clock-Driven Numerical Sequences

The Rhythm of State

Registers store state, but counters transform it. A counter is a specialized state machine driven by a clock, moving deterministically through a sequence of numerical states. By cascading flip-flops asynchronously, we create simple, slow Ripple Counters. By driving them all synchronously, we create precise, high-speed machines capable of frequency division, event tallying, and digital timing.

CLOCK → FLIP-FLOP STATE → STATE TRANSITION → NEXT BINARY STATE → REPEATED CLOCKING → STATE SEQUENCE → COUNT

The 18 Progression Nodes

Ontological Mapping: From Ripple to Ring

GROUP 01

Counter Fundamentals

  • Counter as sequential circuit
  • Flip-flop based storage
  • Clock-driven state changes
  • Number of states (Modulus)
GROUP 02

Binary Concept

MSB
BIT1
LSB
  • Binary counting sequence
  • LSB toggles fastest
  • MSB toggles slowest
  • Counting capacity (2^N)
GROUP 03

Asynchronous / Ripple

  • Cascaded flip-flops
  • CLK drives first stage only
  • Outputs drive next clocks
  • Propagation-delay accumulation
GROUP 04

Ripple Operation

CLK
Q0
Q1
  • Toggle sequence timing
  • Frequency division by 2
  • Transient intermediate states
  • Ripple timing diagrams
GROUP 05

Synchronous Counters

  • Common master clock
  • Simultaneous triggering
  • Combinational next-state logic
  • Eliminates ripple delay
GROUP 06

Up Counters

  • Incrementing sequence
  • Binary up-count (0→N)
  • Positive transition logic
  • Reaching terminal count
GROUP 07

Down Counters

  • Decrementing sequence
  • Binary down-count (N→0)
  • Complemented outputs/clocks
  • Reaching zero state
GROUP 08

Up/Down Counters

  • Direction-control input
  • Mode switching logic
  • MUX-based steering
  • Bidirectional counting
GROUP 09

Mod-n Counters

  • MOD number (Modulus)
  • Number of unique states
  • Truncated counting
  • Unused states & Reset
GROUP 10

Decade Counter

  • MOD-10 specific operation
  • Decimal counting (0–9)
  • Reset upon reaching 1010
  • BCD display applications
GROUP 11

Counter Design Flow

  • Determine required states
  • State assignment / diagram
  • Excitation tables (JK, T, D)
  • Next-state K-Map logic
GROUP 12

MOD-n Implementation

  • Start with Natural binary
  • Decode terminal state (NAND)
  • Asynchronous Clear mechanism
  • Custom counting sequences
GROUP 13

Ring Counter

  • Shift-register based
  • One-hot state pattern
  • Circulating single bit
  • Requires Pre-set Initialization
GROUP 14

Johnson Counter

  • Twisted-ring structure
  • Complemented feedback (Q' to D)
  • Walking ring sequence
  • Yields 2N states
GROUP 15

Frequency Division

f
f/2
f/4
  • Counter as clock scaler
  • Divide-by-2 per stage
  • Divide-by-N overall behavior
  • Digital clocks & timing
GROUP 16

Counter Timing

  • Ripple vs Synchronous delay
  • Maximum operating frequency
  • Transient glitches (spikes)
  • Decoding hazards
GROUP 17

Decoding & Control

  • Target state detection
  • Terminal-count logic
  • Enable & Preset controls
  • Sequence termination
FINAL PROTOCOL

18 — Sequential Machine Laboratory

1. STATE DIAGRAM: 0 → 1 → 3 → 2
2. EXCITATION: J0 = Q1', K0 = 1
3. FREQ_OUT = f_CLK / MOD_N
[1] TRACE MODULUS [2] CHECK GLITCHES [3] IDENTIFY RING/JOHNSON [4] DESIGN SYNC LOGIC [5] CALCULATE DELAY

Counters are the first autonomous machines. Once clocked, they drive themselves through a predetermined destiny. By mastering the excitation tables, we learn how to force memory elements to step through any arbitrary sequence, laying the absolute groundwork for Realm 16: Finite State Machines.

SIMULATION RUNNING