Ontological Layer: Mathematical Hardware
Arithmetic Circuits
The Silicon Computation Core
The Mechanics of Mathematics
Binary arithmetic in Realm 03 was purely theoretical. Here, it becomes physical. By wiring logic gates together, we build blocks that can physically add and subtract voltage levels. We discover that multi-bit addition creates a catastrophic bottleneck—the ripple carry delay—and engineer advanced look-ahead logic to bypass it, forming the foundation of the modern ALU.
The 14 Arithmetic Nodes
Ontological Mapping: From Bits to the ALU
Hardware Foundations
- 01.1 Binary arithmetic in hardware
- 01.2 Inputs → operation → outputs
- 01.3 Sum & Difference
- 01.5 Carry & Borrow Concepts
Half Adder
- 02.1 Two binary inputs (A, B)
- 02.6 XOR for Sum (A ⊕ B)
- 02.7 AND for Carry (A · B)
- Incapable of receiving external carry
Full Adder
- 03.3 Integrates Carry-In (Cin)
- 03.8 Two Half-Adders + OR Gate
- Sum = A ⊕ B ⊕ Cin
- Cout = AB + Cin(A ⊕ B)
Binary Addition
- 04.1 Bit-by-bit physical addition
- 04.3 Carry propagation dependency
- 04.4 LSB → MSB sequential operation
- Foundation for cascading adders
Ripple-Carry Adder
- 05.1 Cascaded Full Adders (N-bit)
- 05.3 Carry ripples through stages
- 05.4 Severe propagation delay
- 05.6 Linear O(N) performance limit
Carry Look-Ahead
- 06.3 Generate (G) & Propagate (P)
- 06.4 Parallel carry computation
- 06.5 Drastically reduced O(1) delay
- Higher hardware complexity trade-off
Half Subtractor
- 07.2 Difference output (A ⊕ B)
- 07.3 Borrow output (A' · B)
- Requires inversion of Minuend
- Incapable of receiving external borrow
Full Subtractor
- 08.3 Integrates Borrow-In (Bin)
- Difference = A ⊕ B ⊕ Bin
- Bout = A'B + Bin(A ⊕ B)'
- Two Half-Subtractors + OR Gate
Binary Subtraction
- 09.1 Borrow mechanism logic
- 09.3 Multi-bit subtraction
- Physical hardware vs 2's Complement
- Why direct subtractors are rare
Adder-Subtractor
- 10.1 Shared arithmetic hardware
- 10.2 XOR-controlled inversion (B ⊕ M)
- 10.3 Mode control bit (M=0 Add, M=1 Sub)
- Implements 2's-complement subtraction
Multi-Bit Arithmetic
- 11.1 N-bit architecture stacking
- 11.4 Signed vs 11.5 Unsigned processing
- 11.6 Overflow detection boundaries
- Sign-extension considerations
Arithmetic Logic
- 12.2 XOR → addition/comparison
- 12.3 AND → carry generation
- 12.4 Arithmetic block construction
- 12.5 The ALU Foundation
Performance Limits
- 13.1 Gate propagation delay
- 13.3 Ripple-carry cascading bottleneck
- 13.4 Carry look-ahead speed advantage
- 13.5 Speed vs hardware complexity
14 — The Arithmetic Hardware Laboratory
Arithmetic circuits represent the synthesis of everything learned so far. By using XOR gates to calculate sums and AND/OR gates to manage carries, we transition from simple logical decisions (Realm 05) into dynamic mathematical processing capable of driving an entire computational unit.