Ontological Layer: Physical Data Storage
The Memory Hierarchy
The Layers Between Thought and Storage
The Impossible Memory
Computer architects want an impossible paradox: memory that is as fast as a CPU register, as massive as a hard drive, and costs nothing. Because no single physical technology can do this, we build a pyramid. Fast, expensive memory sits at the top near the CPU, caching data pulled from the slower, cheaper, massive storage at the bottom. Realm 05 explores the physical realities, mapping strategies, and access mathematics that make this illusion of infinite, instantaneous memory possible.
The 12 Memory Chambers
Ontological Mapping: From Registers to Persistent Storage
The Idea of Memory
- Storage of data and instructions
- Addressable memory locations
- Read and Write operations
- Latency vs Bandwidth basics
Memory Hierarchy
- Speed vs Capacity vs Cost trade-off
- Registers → Cache → RAM → Storage
- Distance from the CPU core
- The illusion of fast, infinite memory
Access & Addressing
- Address bus width determines capacity
- Data bus width determines throughput
- Byte-addressable vs Word-addressable
- Read/Write control signals
Cache Memory
- SRAM buffer close to CPU
- L1, L2, L3 architectural levels
- Cache Hits (Fast) vs Misses (Penalty)
- Unified vs Split (Instruction/Data)
Locality of Reference
- Why small caches work effectively
- Temporal Locality (Reuse same item)
- Spatial Locality (Use nearby items)
- Sequential code execution loops
Cache Mapping
- Direct Mapped (1 slot per block)
- Fully Associative (Any slot)
- N-Way Set Associative (Hybrid)
- Tag comparison and Indexing
Policies
- Replacement: LRU, FIFO, Random
- Write-Through (Sync immediately)
- Write-Back (Sync only on eviction)
- Dirty bits and write allocation
RAM Technologies
- SRAM (Flip-flops, fast, expensive, Cache)
- DRAM (Capacitors, slow, cheap, Main RAM)
- The need for constant DRAM refresh
- Volatile nature of RAM
Non-Volatile Memory
- ROM (Permanent firmware)
- EEPROM (Electrically erasable)
- Flash Memory (Block-erasable, SSDs)
- Read-only vs Reprogrammable constraints
Memory Expansion
- Word width expansion (Parallel chips)
- Capacity expansion (Address decoding)
- Memory Banks and Modules
- Interleaved memory for bandwidth
Performance & ECC
- Average Memory Access Time (AMAT)
- Miss Penalty impact calculations
- Soft errors vs Hard faults
- Error Correcting Codes (ECC)
12 — AMAT & Mapping Laboratory
You now understand the physical reality of memory: it is tiered, structured, and carefully managed by hardware to hide its inherent slowness. But how does an operating system safely share this limited physical RAM among dozens of running programs simultaneously? This leads directly into Realm 06: Virtual Memory.