Ontological Layer: The Neural Pathways
The Interconnection
The Highways Through Which the Machine Speaks
Binding the Fragments
A brilliant CPU, an infinite memory, and rapid I/O devices are utterly useless if they are isolated. They must communicate. Realm 08 reveals the intricate highways of the computer—the System Bus and modern Interconnect Fabrics. We dissect the fundamental lines of communication: Data (What), Address (Where), and Control (How). We explore how components fiercely negotiate for access via Arbitration, the laws of synchronous timing, and how modern architecture is abandoning the shared bus for scalable, point-to-point networks.
The 12 Interconnect Chambers
Ontological Mapping: Buses, Links, and Arbitration
The Interconnection Problem
- Why components need to communicate
- Data transfer vs control coordination
- Shared vs dedicated pathways
- The necessity of a common standard
System Bus Architecture
- Shared communication pathway concept
- Connecting CPU, Main Memory, and I/O
- Logical grouping of electrical signals
- The classic Von Neumann bottleneck
Data, Address, Control
- Data Bus: The payload being transferred
- Address Bus: Identifies source/destination
- Control Bus: Specifies the action (Read/Write)
- Width constraints define system limits
Bus Transactions
- Master requests bus access
- Master asserts Address and Command
- Data transfer occurs (Read/Write)
- Slave acknowledges completion
Arbitration & Masters
- Resolving contention between multiple masters
- CPU vs DMA Controllers vs I/O
- Centralized vs Distributed Arbitration
- Daisy-Chain vs Fixed Priority
Synchronous / Asynchronous
- Sync: Global clock dictates transfer edges
- Async: Handshaking protocol (Req/Ack)
- Handling variable speed devices
- Clock skew across long distances
Serial vs Parallel
- Parallel: Multiple bits per cycle, clock skew issues
- Serial: One bit per cycle, ultra-high frequency
- Why modern buses shifted to Serial (PCIe, SATA)
- Simplex vs Half-Duplex vs Full-Duplex
Interfaces & Protocols
- Rules governing communication syntax
- Packet-based interconnects (PCIe)
- Headers, Payloads, and CRC error checking
- USB, SATA, Ethernet abstraction layers
DMA & Interconnect
- DMA temporarily usurps Bus Master role
- Cycle stealing vs Block burst modes
- Interrupt lines for CPU notification
- Signaling an event vs transferring data
Bandwidth & Throughput
- Bandwidth: Maximum theoretical capacity
- Latency: Delay before data arrives
- Throughput: Actual achieved rate
- Contention and Queueing overhead
Point-to-Point Fabrics
- Moving away from shared broadcast wires
- Switched Fabric and Crossbar topologies
- PCI Express lanes and link aggregation
- Network-on-Chip (NoC) for many-core
12 — The Interconnect Laboratory
The CPU computes, memory stores, and I/O communicates—but the interconnection is the vital circulatory system that allows them to exchange information. With the entire hardware architecture now mapped, we face the ultimate question: How can the processor execute *more* instructions, *faster*? This prepares us for Realm 09: Pipelining & Performance.