Memory Management

The Illusion of Infinite Memory

The Grand Illusion

Physical RAM is finite, rigid, and shared among dozens of competing processes. To prevent chaos, the Operating System and the MMU collude to project a grand illusion: Virtual Memory. Every program is lied to, given a pristine, continuous "Virtual Address Space" starting at zero. Realm 06 explores how these fake addresses are translated into physical reality on the fly via Page Tables, how the TLB accelerates the lie, and how Demand Paging allows programs larger than physical RAM to execute flawlessly.

PROGRAM EXECUTES → VIRTUAL ADDRESS → TLB / MMU TRANSLATION → HIT → PHYSICAL RAM vs PAGE FAULT (MISS) → OS TRAP → LOAD FROM DISK ↻

The 12 Management Chambers

Ontological Mapping: From Fragmentation to Translation

CHAMBER 01

The Management Problem

Multiple processes sharing limited RAM
Dynamic allocation and deallocation
Ensuring process isolation/protection
The need for efficient utilization

CHAMBER 02

Logical vs Physical

Logical (Virtual): CPU generated, program view
Physical: Actual hardware RAM location
Address space separation
Relocation transparency for programs

CHAMBER 03

MMU & Translation

Memory Management Unit (Hardware)
On-the-fly execution translation
Hardware and OS cooperation
Base and Limit register concepts

CHAMBER 04

Contiguous & Fragmentation

Older model: Entire process in contiguous RAM
Internal Fragmentation: Wasted space inside a block
External Fragmentation: Free space scattered in small holes
First-Fit, Best-Fit, Compaction

CHAMBER 05

Paging Concepts

Breaks contiguity requirement
Pages: Fixed-size logical blocks
Frames: Fixed-size physical blocks
Eliminates external fragmentation

CHAMBER 06

Page Tables

Data structure storing Page → Frame maps
Page Table Entry (PTE): Frame #, Valid, Dirty
Virtual Address = Page Number + Offset
Multi-level hierarchical page tables

CHAMBER 07

The TLB

Translation Lookaside Buffer (Hardware Cache)
Avoids slow RAM access for Page Table lookup
TLB Hit: Immediate physical address
TLB Miss: Must walk the Page Table in RAM

CHAMBER 08

Virtual Memory

Logical memory separated from physical residency
Allows programs larger than physical RAM
Demand Paging: Load pages only when accessed
Resident (in RAM) vs Non-Resident (on Disk)

CHAMBER 09

Page Faults

Trap to OS when page is not present (Miss)
OS suspends process, loads page from disk
Page Replacement: Evicting a victim frame
Policies: FIFO, LRU, Optimal (Belady's Anomaly)

CHAMBER 10

Segmentation & Sharing

Segmentation: Logical grouping (Code, Data, Stack)
Variable sizes vs Paging's fixed sizes
Memory Sharing: Common pages mapped into multiple PTs
Copy-on-Write optimization

CHAMBER 11

Thrashing & Perf

Protection bits (R/W/X, Kernel/User)
Thrashing: Excessive paging, CPU idle
Working Set Model: Tracking active pages
Effective Access Time calculations

FINAL PROTOCOL

12 — The Virtualization Laboratory

1. VA: 0x40A2 (Page: 4, Offset: 0xA2)

2. PT[4] -> Frame 9 (Valid=1)

3. PA = (9 * 256) + 0xA2 = 0x9A2

[1] CALC PAGE/FRAME SIZES [2] TRACE TLB PATH [3] RESOLVE FAULTS [4] EXECUTE LRU REPLACEMENT [5] DETECT THRASHING

You have seen how the OS wields the MMU to create a safe, isolated, and seemingly infinite playground for every application. But how does software actually communicate with the outside world? It must break out of RAM. This leads us directly to Realm 07: The I/O System.

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