Ontological Layer: The External Interface

Input / Output Architecture

The Machine Meets the Outside World

Breaking the Sandbox

A computer with only a CPU and memory is a deaf, blind, and mute calculator. To possess utility, it must interact with chaotic, asynchronous, and incredibly slow external physical reality. Realm 07 documents this necessary breach. We study how Controllers abstract physical hardware, how Interrupts allow the CPU to ignore devices until necessary, and how Direct Memory Access (DMA) cuts the CPU out of bulk transfers entirely, establishing a high-speed conduit directly into RAM.

PROGRAMMED → CPU POLLS DEVICE | INTERRUPT → DEVICE SIGNALS CPU | DMA → DEVICE WRITES RAM DIRECTLY

The 12 Communication Chambers

Ontological Mapping: From Polling to DMA

CHAMBER 01

The I/O Problem

Data exchange with external environments
Massive speed disparities (CPU vs Disk)
Variety of interfaces and data formats
Human-readable vs Machine-readable

CHAMBER 02

Devices & Controllers

Controller: Electronic logic interface
Device: Physical mechanical/sensor hardware
Standardizes hardware variations for the bus
Handles low-level error detection

CHAMBER 03

Device Registers

STAT

CTRL

DATA

Status Register: Ready, Busy, Error
Control Register: CPU commands to device
Data Register: Holding buffer for transfer
The logical window into physical hardware

CHAMBER 04

Programmed I/O

CPU directly manages every transfer step
Polling: Repeatedly checking Status Register
Wasteful: CPU stalled waiting for slow devices
Simple hardware implementation

CHAMBER 05

Interrupt-Driven I/O

Device hardware signals CPU when ready
CPU performs other tasks instead of polling
Context switch to Interrupt Service Routine
Restores previous state upon completion

CHAMBER 06

Interrupt Routing

Interrupt Controller: Prioritizes multiple IRQs
Maskable vs Non-Maskable Interrupts (NMI)
Interrupt Vector: Maps IRQ line to software
Vector Table holds handler memory addresses

CHAMBER 07

Direct Memory Access

Bypasses CPU for bulk data transfers
DMA Controller takes temporary bus mastery
Streams data straight from Device to RAM
Cycle Stealing vs Block Burst modes

CHAMBER 08

I/O Addressing

Memory-Mapped I/O: Device registers share RAM addresses
Isolated (Port) I/O: Separate address space
Standard memory instructions (MOV) vs special (IN/OUT)
Allows easy device abstraction in C/Assembly

CHAMBER 09

Buffers & Queues

Absorbs extreme data-rate mismatches
Single vs Double Buffering (Ping-Pong)
Circular Buffers (Ring) for continuous streams
Pending I/O requests queued by the OS

CHAMBER 10

Drivers & Software

Device Driver: Hardware-specific software glue
Translates OS generic calls to raw register bits
Hides specific hardware quirks from User Apps
Executes in privileged kernel mode

CHAMBER 11

Real-Time Constraints

I/O Latency, Throughput, and CPU Overhead
Hard Real-Time: Missing deadline is a system failure
Soft Real-Time: Missing deadline degrades quality
Interrupt coalescing to reduce CPU thrashing

FINAL PROTOCOL

12 — The Transfer Laboratory

MODE: PROGRAMMED_IO -> CPU UTIL: 99% (WASTE)

MODE: INTERRUPT_DRIVEN -> CPU UTIL: 12% (SWITCH COST)

IRQ DETECTED: TRAP TO ISR...

MODE: DMA_BURST -> RAM[0xA0] <=== DISK (CPU FREE)

[1] POLL STATUS [2] TRIGGER IRQ [3] TRACE VECTOR [4] INITIALIZE DMA REGISTERS [5] MEASURE LATENCY

We now understand the CPU, Memory, and the external Devices. But how are these disparate components physically wired together? How do electrical signals traverse the motherboard without colliding? This systemic physical integration is the domain of Realm 08: System Interconnection & Buses.

INTERRUPT DIAGNOSTIC RUNNING