Ontological Layer: Electrostatic Control

FET / JFET / MOSFET

The Architecture of the Electric Field

Voltage-Controlled Conduction

While the BJT relies on current injection and bipolar carrier interaction, the Field-Effect Transistor represents a completely different philosophy of control. By applying a voltage to an insulated gate, an electric field penetrates the semiconductor, drawing carriers to the surface to form a conductive channel. It is pure electrostatic control—the foundation of modern high-density digital and analog circuits.

ELECTRIC FIELD → ELECTROSTATIC CONTROL → CHANNEL CONDUCTIVITY → DRAIN CURRENT → DEVICE CHARACTERISTIC → BIAS / REGION → AMPLIFICATION / SWITCHING

The 86 Field-Effect Nodes

Ontological Mapping: Nodes 01 - 86

GROUP 01-08

Concept & Terminals

01 FET Concept & Principle
03 Voltage-Controlled Device
04 Electric-Field Control
05 Terminals: Source, Gate, Drain
08 Types: JFET vs MOSFET

GROUP 09-16

JFET Architecture

09-11 JFET Structure (n/p channel)
12 Gate Junction & 13 Bias
14 Channel Control
15 Pinch-Off Condition
16 Cutoff State

GROUP 17-22

JFET Characteristics

17 V-I Characteristics
18 Drain Characteristics
19 Transfer Characteristics
20 Shockley Equation
21 Transconductance

GROUP 23-33

MOS Cap & Inversion

25 Metal-Oxide-Semiconductor
27 MOS Capacitor Foundation
28 Threshold Voltage (Vth)
31 Accumulation & 32 Depletion
33 Inversion Layer Formation

GROUP 34-40

MOSFET Types

34 Enhancement MOSFET
35 Depletion MOSFET
36-37 N-Channel vs P-Channel
38 Body/Substrate Connection
39-40 Body Effect Relationship

GROUP 41

Operating Regions

41 Defining the Three Regions
Cutoff (Switch OFF)
Triode / Linear (Voltage Control)
Saturation (Constant Current)

GROUP 42-49

Characteristics & Math

42-44 V-I & Transfer Curves
46 Drain Current Equations
47 Transconductance (gm)
48 Output Resistance (ro)
49 Channel-Length Modulation

GROUP 50-57

Non-Idealities & Freq

50 MOSFET Capacitances (Cgs, Cgd)
52 Subthreshold Conduction
53 Short-Channel Effects
54 Mobility Deg. / 55 Velocity Sat.
56 DIBL & 57 Breakdown

GROUP 58-62

Switching & CMOS

58 MOSFET Switching Times
60 Charge Storage Effects
61 Power MOSFETs (VMOS, LDMOS)
62 CMOS Relationship (NMOS+PMOS)

GROUP 63-67

Configurations

63 Biasing & 64 Small-Signal Models
65 Common-Source (CS)
66 Common-Gate (CG)
67 Common-Drain (CD / Follower)

GROUP 68-71

Device Comparisons

BJT

FET

68 JFET vs MOSFET Concepts
69 Enhancement vs Depletion Modes
70 N-Channel vs P-Channel perf.
71 FET vs BJT (Voltage vs Current Ctrl)

FINAL PROTOCOL

12 — FET Analytical Laboratory

ID = ½μCox(W/L)(VGS - VTH)²

gm = ∂ID / ∂VGS = μCox(W/L)(VGS - VTH)

ro = 1 / (λID)

[1] CHECK VGS > VTH [2] DETERMINE REGION [3] CALCULATE ID [4] EXTRACT gm & ro [5] SMALL-SIGNAL ANALYSIS

Executing the mathematics of the Field-Effect Transistor. From calculating drain current in saturation to extracting transconductance parameters, establishing the foundation for CMOS logic design and analog amplification.

SIMULATION RUNNING